clk/qcom/mdss: update power-up sequence for DSI 7nm PLL

Add the required programming to assert the reset for the PHY
digital domain as part of the PLL power up sequence. This is
required to support scenarios where the PHY digital and analog
supply rails may get collapsed in idle screen.

Change-Id: I20c3f0576253674d8bc2ce01cbb23c221924a13f
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>