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Commit 65398511 authored by Tomi Valkeinen's avatar Tomi Valkeinen
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OMAPDSS: DISPC: cleanup lcd and digit enable



dispc.c's functions to enable LCD and DIGIT outputs can be cleaned up a
bit by using common functions to set the enable bit and to check if the
output is enabled.

Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
parent 16bf20c7
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+10 −17
Original line number Diff line number Diff line
@@ -2590,13 +2590,18 @@ static void dispc_disable_isr(void *data, u32 mask)
	complete(compl);
}

static void _enable_lcd_out(enum omap_channel channel, bool enable)
static void _enable_mgr_out(enum omap_channel channel, bool enable)
{
	mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable);
	/* flush posted write */
	mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
}

bool dispc_mgr_is_enabled(enum omap_channel channel)
{
	return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
}

static void dispc_mgr_enable_lcd_out(enum omap_channel channel, bool enable)
{
	struct completion frame_done_completion;
@@ -2607,7 +2612,7 @@ static void dispc_mgr_enable_lcd_out(enum omap_channel channel, bool enable)
	/* When we disable LCD output, we need to wait until frame is done.
	 * Otherwise the DSS is still working, and turning off the clocks
	 * prevents DSS from going to OFF mode */
	is_on = mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
	is_on = dispc_mgr_is_enabled(channel);

	irq = mgr_desc[channel].framedone_irq;

@@ -2621,7 +2626,7 @@ static void dispc_mgr_enable_lcd_out(enum omap_channel channel, bool enable)
			DSSERR("failed to register FRAMEDONE isr\n");
	}

	_enable_lcd_out(channel, enable);
	_enable_mgr_out(channel, enable);

	if (!enable && is_on) {
		if (!wait_for_completion_timeout(&frame_done_completion,
@@ -2636,13 +2641,6 @@ static void dispc_mgr_enable_lcd_out(enum omap_channel channel, bool enable)
	}
}

static void _enable_digit_out(bool enable)
{
	REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
	/* flush posted write */
	dispc_read_reg(DISPC_CONTROL);
}

static void dispc_mgr_enable_digit_out(bool enable)
{
	struct completion frame_done_completion;
@@ -2651,7 +2649,7 @@ static void dispc_mgr_enable_digit_out(bool enable)
	u32 irq_mask;
	int num_irqs;

	if (REG_GET(DISPC_CONTROL, 1, 1) == enable)
	if (dispc_mgr_is_enabled(OMAP_DSS_CHANNEL_DIGIT) == enable)
		return;

	src = dss_get_hdmi_venc_clk_source();
@@ -2688,7 +2686,7 @@ static void dispc_mgr_enable_digit_out(bool enable)
	if (r)
		DSSERR("failed to register %x isr\n", irq_mask);

	_enable_digit_out(enable);
	_enable_mgr_out(OMAP_DSS_CHANNEL_DIGIT, enable);

	for (i = 0; i < num_irqs; ++i) {
		if (!wait_for_completion_timeout(&frame_done_completion,
@@ -2712,11 +2710,6 @@ static void dispc_mgr_enable_digit_out(bool enable)
	}
}

bool dispc_mgr_is_enabled(enum omap_channel channel)
{
	return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
}

void dispc_mgr_enable(enum omap_channel channel, bool enable)
{
	if (dss_mgr_is_lcd(channel))