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Commit 65205701 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "Merge commit '80cd59db' into dev/msm-4.14-display"

parents aee5aeb2 853bfa63

Documentation/arm64/silicon-errata.txt

+1 −0
Original line number Original line Diff line number Diff line
@@ -56,6 +56,7 @@ stable kernels. 
| ARM            | Cortex-A72      | #853709         | N/A                         |

| ARM            | Cortex-A72      | #853709         | N/A                         |

| ARM            | Cortex-A73      | #858921         | ARM64_ERRATUM_858921        |

| ARM            | Cortex-A73      | #858921         | ARM64_ERRATUM_858921        |

| ARM            | Cortex-A55      | #1024718        | ARM64_ERRATUM_1024718       |

| ARM            | Cortex-A55      | #1024718        | ARM64_ERRATUM_1024718       |

| ARM            | Cortex-A76      | #1286807        | ARM64_ERRATUM_1286807       |

| ARM            | MMU-500         | #841119,#826419 | N/A                         |

| ARM            | MMU-500         | #841119,#826419 | N/A                         |

|                |                 |                 |                             |

|                |                 |                 |                             |

| Cavium         | ThunderX ITS    | #22375, #24313  | CAVIUM_ERRATUM_22375        |

| Cavium         | ThunderX ITS    | #22375, #24313  | CAVIUM_ERRATUM_22375        |

Documentation/devicetree/bindings/arm/msm/msm.txt

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@@ -44,6 +44,9 @@ SoCs: 
- SM8150

- SM8150

  compatible = "qcom,sm8150"

  compatible = "qcom,sm8150"





- SM8150P

  compatible = "qcom,sm8150p"



- SDMSHRIKE

- SDMSHRIKE

  compatible = "qcom,sdmshrike"

  compatible = "qcom,sdmshrike"

Documentation/devicetree/bindings/arm/msm/qrtr_fifo_xprt.txt

0 → 100644
+25 −0
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Qualcomm Technologies, Inc. IPC Router FIFO Transport



Required properties:

- compatible:	should be "qcom,ipcr_fifo_xprt"

- reg:		the irq register to raise an interrupt

- interrupts:	the receiving interrupt line

- qcom,ipc-shm:	Reference to shared memory phandle



Example:



	fifo_vipc_irq@176 {

		compatible = "qcom,ipcr-fifo-xprt";

		reg = <0x176>;

		interrupts = <0x0 0x142 0x1>;

		qcom,ipc-shm = <&ipc-shm>;

	};



	ipc-shm: shared-buffer@85af7000 {

		compatible = "qcom,hypervisor-shared-memory";

		phandle = <0x1e4>;

		reg = <0x0 0x85af7000 0x0 0x9000>;

		label = "ipc_shm";

		qcom,tx-is-first;

	};

Documentation/devicetree/bindings/bus/mhi.txt

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@@ -144,6 +144,13 @@ mhi channel node properties: 
  Definition: Time sensitive data channel, host should process all pending data

  Definition: Time sensitive data channel, host should process all pending data

	before system suspend.

	before system suspend.





- mhi,chan-type

  Usage: optional

  Value type: <u32>

  Definition: By default, chan-type is same as 'chan,dir' property except

	in some special channels, chan type supplement chan direction.

	3 = default no direction, or inbound coalesced channel



==========================

==========================

mhi event node properties:

mhi event node properties:

==========================

==========================

Documentation/devicetree/bindings/media/video/msm-cam-cpas.txt

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@@ -169,6 +169,16 @@ First Level Node - CAM CPAS device 
  Definition: Bool property specifying whether Clients are connected

  Definition: Bool property specifying whether Clients are connected

	through CAMNOC for AXI access.

	through CAMNOC for AXI access.





- qcom,cam-cx-ipeak:

  Usage: optional

  Value type: <phandle bit>

	phandle - phandle of CX Ipeak device node

	bit     - Every bit corresponds to a client of CX Ipeak

  Definition: CX Ipeak is a mitigation scheme which throttles camera frequency

	if all the clients are running at their respective threshold

	frequencies to limit CX peak current.

	driver in the relevant register.



===================================================================

===================================================================

Third Level Node - CAM AXI Port properties

Third Level Node - CAM AXI Port properties

===================================================================

===================================================================
@@ -226,6 +236,7 @@ Example: 
		src-clock-name = "slow_ahb_clk_src";

		src-clock-name = "slow_ahb_clk_src";

		clock-rates = <0 0 0 0 80000000 0>;

		clock-rates = <0 0 0 0 80000000 0>;

		clock-cntl-level = "turbo";

		clock-cntl-level = "turbo";

		qcom,cam-cx-ipeak = <&cx_ipeak_lm 2>;

		control-camnoc-axi-clk;

		control-camnoc-axi-clk;

		camnoc-bus-width = <32>;

		camnoc-bus-width = <32>;

		camnoc-axi-clk-bw-margin-perc = <10>;

		camnoc-axi-clk-bw-margin-perc = <10>;