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Commit 6509f28e authored by Saranya Chidura's avatar Saranya Chidura Committed by Rama Aparna Mallavarapu
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soc: qcom: Fix the programming of DCC registers for CRC,DCCV2 



For CRC, few DCC registers are not programmed with the current
configuration. program LL and FD base registers with the chosen
linked list configuration. And also fix the segmentation
fault caused by default linked list at show_config.

Change-Id: I71c5768f5d799053361ceba771f3e3d768394867
Signed-off-by: default avatarSaranya Chidura <schidura@codeaurora.org>
parent 588b84d2

drivers/soc/qcom/dcc_v2.c

+9 −8
Original line number Diff line number Diff line
@@ -554,14 +554,12 @@ static int dcc_enable(struct dcc_drvdata *drvdata) 
			goto err;

		}



		/* 3. If in capture mode program DCC_RAM_CFG reg */

		if (drvdata->func_type[list] == DCC_FUNC_TYPE_CAPTURE) {

		/* 3. program DCC_RAM_CFG reg */

		dcc_writel(drvdata, ram_cfg_base +

			   drvdata->ram_offset/4, DCC_LL_BASE(list));

		dcc_writel(drvdata, drvdata->ram_start +

			   drvdata->ram_offset/4, DCC_FD_BASE(list));

		dcc_writel(drvdata, 0xFFF, DCC_LL_TIMEOUT(list));

		}



		/* 4. Configure trigger, data sink and function type */

		dcc_writel(drvdata, BIT(9) | ((drvdata->cti_trig << 8) |
@@ -813,6 +811,9 @@ static ssize_t dcc_show_config(struct device *dev, 


	buf[0] = '\0';



	if (drvdata->curr_list >= DCC_MAX_LINK_LIST)

		return -EINVAL;



	mutex_lock(&drvdata->mutex);

	list_for_each_entry(entry,

			    &drvdata->cfg_head[drvdata->curr_list], list) {