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Commit 64bfca5c authored by Ralf Baechle's avatar Ralf Baechle
Browse files

[MIPS] Cache: Provide more information on cache policy on bootup. 



This should help making bug reports for the gadzillion of cores with all
their configuration and synthesis options more useful.

Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 985c30ef

arch/mips/mm/c-r4k.c

+7 −3
Original line number Diff line number Diff line
@@ -983,11 +983,15 @@ static void __init probe_pcache(void) 


	printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",

	       icache_size >> 10,

	       cpu_has_vtag_icache ? "virtually tagged" : "physically tagged",

	       cpu_has_vtag_icache ? "VIVT" : "VIPT",

	       way_string[c->icache.ways], c->icache.linesz);



	printk("Primary data cache %ldkB, %s, linesize %d bytes.\n",

	       dcache_size >> 10, way_string[c->dcache.ways], c->dcache.linesz);

	printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n",

	       dcache_size >> 10, way_string[c->dcache.ways],

	       (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT",

	       (c->dcache.flags & MIPS_CACHE_ALIASES) ?

			"cache aliases" : "no aliases",

	       c->dcache.linesz);

}



/*