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Commit 647a729f authored by Saranya Chidura's avatar Saranya Chidura
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ARM: dts: msm: Fix the DCC SRAM address in qcs405 



HLOS configures DCC SRAM from a particular
offset to avoid loss of data of other clients.
Fix the SRAM address for QCS405.

Change-Id: Iba28971e71512d292e56a1eedd42889700f20865
Signed-off-by: default avatarSaranya Chidura <schidura@codeaurora.org>
parent a60934ca

arch/arm64/boot/dts/qcom/qcs405.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -365,7 +365,7 @@ 
	dcc: dcc_v2@b2000 {

		compatible = "qcom,dcc-v2";

		reg = <0x000b2000 0x1000>,

		      <0x000bf800 0x800>;

		      <0x000bfc00 0x400>;



		clocks = <&clock_gcc GCC_DCC_CLK>;

		clock-names = "dcc_clk";