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Commit 6464c0fa authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add DT properties to enable DP on sm6150 target"

parents fe619d57 99dfab2c

Documentation/devicetree/bindings/fb/mdss-pll.txt

+2 −1
Original line number Diff line number Diff line
@@ -18,7 +18,8 @@ Required properties: 
                        "qcom,mdss_dsi_pll_10nm",  "qcom,mdss_dp_pll_8998",

                        "qcom,mdss_hdmi_pll_8998", "qcom,mdss_dp_pll_10nm",

                        "qcom,mdss_dsi_pll_7nm",   "qcom,mdss_dp_pll_7nm",

			"qcom,mdss_dsi_pll_28lpm", "qcom,mdss_dsi_pll_14nm"

			"qcom,mdss_dsi_pll_28lpm", "qcom,mdss_dsi_pll_14nm",

			"qcom,mdss_dp_pll_14nm"

- cell-index:		Specifies the controller used

- reg:			offset and length of the register set for the device.

- reg-names :		names to refer to register sets related to this device

arch/arm64/boot/dts/qcom/sm6150-audio.dtsi

+10 −0
Original line number Diff line number Diff line
@@ -145,3 +145,13 @@ 
		elemental-addr = [ff ff ff fe 17 02];

	};

};



&qupv3_se3_i2c {

	status = "ok";

	fsa4480: fsa4480@43 {

		compatible = "qcom,fsa4480-i2c";

		reg = <0x43>;

		pinctrl-names = "default";

		pinctrl-0 = <&fsa_usbc_ana_en>;

	};

};

arch/arm64/boot/dts/qcom/sm6150-pinctrl.dtsi

+70 −0
Original line number Diff line number Diff line
@@ -591,6 +591,22 @@ 
			};

		};



		fsa_usbc_ana_en_n@114 {

			fsa_usbc_ana_en: fsa_usbc_ana_en {

				mux {

					pins = "gpio114";

					function = "gpio";

				};



				config {

					pins = "gpio114";

					drive-strength = <2>;

					bias-disable;

					output-low;

				};

			};

		};



		pmx_sde_te {

			sde_te_active: sde_te_active {

				mux {
@@ -619,6 +635,60 @@ 
			};

		};



		sde_dp_usbplug_cc_active: sde_dp_usbplug_cc_active {

			mux {

				pins = "gpio104";

				function = "gpio";

			};



			config {

				pins = "gpio104";

				bias-disable;

				drive-strength = <16>;

			};

		};



		sde_dp_usbplug_cc_suspend: sde_dp_usbplug_cc_suspend {

			mux {

				pins = "gpio104";

				function = "gpio";

			};



			config {

				pins = "gpio104";

				bias-pull-down;

				drive-strength = <2>;

			};

		};



		sde_dp_switch_active: sde_dp_switch_active {

			mux {

				pins = "gpio49";

				function = "gpio";

			};



			config {

				pins = "gpio49";

				bias-pull-up;		/* pull up */

				drive-strength = <2>;

			};

		};



		sde_dp_switch_suspend: sde_dp_switch_suspend {

			mux {

				pins = "gpio49";

				function = "gpio";

			};



			config {

				pins = "gpio49";

				bias-pull-down;

				drive-strength = <2>;

			};

		};







		/* SDC pin type */

		sdc1_clk_on: sdc1_clk_on {

			config {

arch/arm64/boot/dts/qcom/sm6150-sde-display.dtsi

+4 −7
Original line number Diff line number Diff line
@@ -155,17 +155,14 @@ 
		label = "wb_display";

	};



	ext_disp: qcom,msm-ext-disp {

		compatible = "qcom,msm-ext-disp";



		ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx {

			compatible = "qcom,msm-ext-disp-audio-codec-rx";

		};

};



&sde_dp {

	qcom,dp-usbpd-detection = <&pm6150_pdphy>;

};



&mdss_mdp {

	connectors = <&sde_rscc &sde_wb &sde_dsi>;

	connectors = <&sde_rscc &sde_wb &sde_dp &sde_dsi>;

};



&dsi_sim_vid {

arch/arm64/boot/dts/qcom/sm6150-sde-pll.dtsi

+23 −10
Original line number Diff line number Diff line
@@ -39,17 +39,16 @@ 
		};

	};



	mdss_dp_pll: qcom,mdss_dp_pll@c011000 {

		status = "disabled";

		compatible = "qcom,mdss_dp_pll_7nm";

	mdss_dp_pll: qcom,mdss_dp_pll@88e9000 {

		compatible = "qcom,mdss_dp_pll_14nm";

		label = "MDSS DP PLL";

		cell-index = <0>;

		#clock-cells = <1>;



		reg = <0x088ea000 0x200>,

		      <0x088eaa00 0x200>,

		      <0x088ea200 0x200>,

		      <0x088ea600 0x200>,

		reg = <0x088e9c00 0x200>,

		      <0x088e9000 0x200>,

		      <0x088e9400 0x200>,

		      <0x088e9800 0x200>,

		      <0xaf03000 0x8>;

		reg-names = "pll_base", "phy_base", "ln_tx0_base",

			"ln_tx1_base", "gdsc_base";
@@ -57,10 +56,24 @@ 
		clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>,

			 <&clock_rpmh RPMH_CXO_CLK>,

			 <&clock_gcc GCC_DISP_AHB_CLK>,

			 <&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>,

			 <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;

			 <&clock_gcc GCC_USB3_SEC_CLKREF_CLK>;

		clock-names = "iface_clk", "ref_clk_src", "gcc_iface",

			"ref_clk", "pipe_clk";

			"ref_clk";

		clock-rate = <0>;



		gdsc-supply = <&mdss_core_gdsc>;

		qcom,platform-supply-entries {

			#address-cells = <1>;

			#size-cells = <0>;



			qcom,platform-supply-entry@0 {

				reg = <0>;

				qcom,supply-name = "gdsc";

				qcom,supply-min-voltage = <0>;

				qcom,supply-max-voltage = <0>;

				qcom,supply-enable-load = <0>;

				qcom,supply-disable-load = <0>;

			};

		};

	};

};