Loading arch/arm64/boot/dts/qcom/trinket.dtsi +5 −4 Original line number Diff line number Diff line Loading @@ -2289,11 +2289,12 @@ operating-points-v2 = <&ddr_bw_opp_table>; }; cpu_cpu_ddr_bwmon: qcom,cpu-cpu-ddr-bwmon@90cd000 { compatible = "qcom,bimc-bwmon5"; reg = <0x90cd000 0x1000>; reg-names = "base"; cpu_cpu_ddr_bwmon: qcom,cpu-cpu-ddr-bwmon@01b8e200 { compatible = "qcom,bimc-bwmon4"; reg = <0x01b8e200 0x100>, <0x01b8e100 0x100>; reg-names = "base", "global_base"; interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>; qcom,mport = <0>; qcom,hw-timer-hz = <19200000>; qcom,target-dev = <&cpu_cpu_ddr_bw>; qcom,count-unit = <0x10000>; Loading Loading
arch/arm64/boot/dts/qcom/trinket.dtsi +5 −4 Original line number Diff line number Diff line Loading @@ -2289,11 +2289,12 @@ operating-points-v2 = <&ddr_bw_opp_table>; }; cpu_cpu_ddr_bwmon: qcom,cpu-cpu-ddr-bwmon@90cd000 { compatible = "qcom,bimc-bwmon5"; reg = <0x90cd000 0x1000>; reg-names = "base"; cpu_cpu_ddr_bwmon: qcom,cpu-cpu-ddr-bwmon@01b8e200 { compatible = "qcom,bimc-bwmon4"; reg = <0x01b8e200 0x100>, <0x01b8e100 0x100>; reg-names = "base", "global_base"; interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>; qcom,mport = <0>; qcom,hw-timer-hz = <19200000>; qcom,target-dev = <&cpu_cpu_ddr_bw>; qcom,count-unit = <0x10000>; Loading