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Commit 6417228b authored by Aravind Venkateswaran's avatar Aravind Venkateswaran Committed by Gerrit - the friendly Code Review server
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drm/msm/dsi-staging: fix idle power collapse exit sequence for PHY v3 



Ensure that the escape clock is turned on prior to reinitializing
the DSI PHY when exiting idle power collapse. This will ensure that
there are no spurious transitions on the lanes after the PHY clamps
are removed.

Change-Id: Ic7ce1af62581b71d2a610b18381c9c57eb80696c
Signed-off-by: default avatarAravind Venkateswaran <aravindh@codeaurora.org>
parent c449fd9e

drivers/gpu/drm/msm/dsi-staging/dsi_catalog.c

+1 −0
Original line number Diff line number Diff line
@@ -216,6 +216,7 @@ static void dsi_catalog_phy_3_0_init(struct dsi_phy_hw *phy) 
	phy->ops.ulps_ops.is_lanes_in_ulps =

		dsi_phy_hw_v3_0_is_lanes_in_ulps;

	phy->ops.phy_timing_val = dsi_phy_hw_timing_val_v3_0;

	phy->ops.clamp_ctrl = dsi_phy_hw_v3_0_clamp_ctrl;

	phy->ops.phy_lane_reset = dsi_phy_hw_v3_0_lane_reset;

	phy->ops.toggle_resync_fifo = dsi_phy_hw_v3_0_toggle_resync_fifo;

}

drivers/gpu/drm/msm/dsi-staging/dsi_catalog.h

+1 −0
Original line number Diff line number Diff line
@@ -102,6 +102,7 @@ u32 dsi_phy_hw_v3_0_get_lanes_in_ulps(struct dsi_phy_hw *phy); 
bool dsi_phy_hw_v3_0_is_lanes_in_ulps(u32 lanes, u32 ulps_lanes);

int dsi_phy_hw_timing_val_v3_0(struct dsi_phy_per_lane_cfgs *timing_cfg,

		u32 *timing_val, u32 size);

void dsi_phy_hw_v3_0_clamp_ctrl(struct dsi_phy_hw *phy, bool enable);

int dsi_phy_hw_v3_0_lane_reset(struct dsi_phy_hw *phy);

void dsi_phy_hw_v3_0_toggle_resync_fifo(struct dsi_phy_hw *phy);

drivers/gpu/drm/msm/dsi-staging/dsi_display.c

+34 −11
Original line number Diff line number Diff line
@@ -1581,9 +1581,19 @@ static int dsi_display_set_clamp(struct dsi_display *display, bool enable) 
	m_ctrl = &display->ctrl[display->cmd_master_idx];

	ulps_enabled = display->ulps_enabled;



	/*

	 * Clamp control can be either through the DSI controller or

	 * the DSI PHY depending on hardware variation

	 */

	rc = dsi_ctrl_set_clamp_state(m_ctrl->ctrl, enable, ulps_enabled);

	if (rc) {

		pr_err("DSI Clamp state change(%d) failed\n", enable);

		pr_err("DSI ctrl clamp state change(%d) failed\n", enable);

		return rc;

	}



	rc = dsi_phy_set_clamp_state(m_ctrl->phy, enable);

	if (rc) {

		pr_err("DSI phy clamp state change(%d) failed\n", enable);

		return rc;

	}
@@ -1597,7 +1607,18 @@ static int dsi_display_set_clamp(struct dsi_display *display, bool enable) 
			pr_err("DSI Clamp state change(%d) failed\n", enable);

			return rc;

		}



		rc = dsi_phy_set_clamp_state(ctrl->phy, enable);

		if (rc) {

			pr_err("DSI phy clamp state change(%d) failed\n",

				enable);

			return rc;

		}



		pr_debug("Clamps %s for ctrl%d\n",

			enable ? "enabled" : "disabled", i);

	}



	display->clamp_enabled = enable;

	return 0;

}
@@ -2900,7 +2921,8 @@ int dsi_pre_clkoff_cb(void *priv, 
	struct dsi_display *display = priv;

	struct dsi_display_ctrl *ctrl;



	if ((clk & DSI_LINK_CLK) && (new_state == DSI_CLK_OFF)) {

	if ((clk & DSI_LINK_CLK) && (new_state == DSI_CLK_OFF) &&

		(l_type && DSI_LINK_LP_CLK)) {

		/*

		 * If ULPS feature is enabled, enter ULPS first.

		 * However, when blanking the panel, we should enter ULPS
@@ -2968,7 +2990,7 @@ int dsi_post_clkon_cb(void *priv, 
	struct dsi_display *display = priv;

	bool mmss_clamp = false;



	if (clk & DSI_CORE_CLK) {

	if ((clk & DSI_LINK_CLK) && (l_type & DSI_LINK_LP_CLK)) {

		mmss_clamp = display->clamp_enabled;

		/*

		 * controller setup is needed if coming out of idle
@@ -2977,6 +2999,13 @@ int dsi_post_clkon_cb(void *priv, 
		if (mmss_clamp)

			dsi_display_ctrl_setup(display);



		/*

		 * Phy setup is needed if coming out of idle

		 * power collapse with clamps enabled.

		 */

		if (display->phy_idle_power_off || mmss_clamp)

			dsi_display_phy_idle_on(display, mmss_clamp);



		if (display->ulps_enabled && mmss_clamp) {

			/*

			 * ULPS Entry Request. This is needed if the lanes were
@@ -3015,17 +3044,11 @@ int dsi_post_clkon_cb(void *priv, 
			goto error;

		}



		/*

		 * Phy setup is needed if coming out of idle

		 * power collapse with clamps enabled.

		 */

		if (display->phy_idle_power_off || mmss_clamp)

			dsi_display_phy_idle_on(display, mmss_clamp);



		/* enable dsi to serve irqs */

		dsi_display_ctrl_irq_update(display, true);

	}

	if (clk & DSI_LINK_CLK) {



	if ((clk & DSI_LINK_CLK) && (l_type & DSI_LINK_HS_CLK)) {

		/*

		 * Toggle the resync FIFO everytime clock changes, except

		 * when cont-splash screen transition is going on.

drivers/gpu/drm/msm/dsi-staging/dsi_phy.c

+20 −0
Original line number Diff line number Diff line
@@ -929,6 +929,26 @@ int dsi_phy_disable(struct msm_dsi_phy *phy) 
	return rc;

}



/**

 * dsi_phy_set_clamp_state() - configure clamps for DSI lanes

 * @phy:        DSI PHY handle.

 * @enable:     boolean to specify clamp enable/disable.

 *

 * Return: error code.

 */

int dsi_phy_set_clamp_state(struct msm_dsi_phy *phy, bool enable)

{

	if (!phy)

		return -EINVAL;



	pr_debug("[%s] enable=%d\n", phy->name, enable);



	if (phy->hw.ops.clamp_ctrl)

		phy->hw.ops.clamp_ctrl(&phy->hw, enable);



	return 0;

}



/**

 * dsi_phy_idle_ctrl() - enable/disable DSI PHY during idle screen

 * @phy:          DSI PHY handle

drivers/gpu/drm/msm/dsi-staging/dsi_phy.h

+9 −0
Original line number Diff line number Diff line
@@ -217,6 +217,15 @@ int dsi_phy_clk_cb_register(struct msm_dsi_phy *phy, 
 */

int dsi_phy_idle_ctrl(struct msm_dsi_phy *phy, bool enable);



/**

 * dsi_phy_set_clamp_state() - configure clamps for DSI lanes

 * @phy:        DSI PHY handle.

 * @enable:     boolean to specify clamp enable/disable.

 *

 * Return: error code.

 */

int dsi_phy_set_clamp_state(struct msm_dsi_phy *phy, bool enable);



/**

 * dsi_phy_set_clk_freq() - set DSI PHY clock frequency setting

 * @phy:          DSI PHY handle