Loading arch/arm64/boot/dts/qcom/trinket-coresight.dtsi +3 −3 Original line number Diff line number Diff line Loading @@ -2214,7 +2214,7 @@ reg-names = "cti-base"; coresight-name = "coresight-cti-wcss_cti0"; status = "disabled"; clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; }; Loading @@ -2226,7 +2226,7 @@ reg-names = "cti-base"; coresight-name = "coresight-cti-wcss_cti1"; status = "disabled"; clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; }; Loading @@ -2238,7 +2238,7 @@ reg-names = "cti-base"; coresight-name = "coresight-cti-wcss_cti2"; status = "disabled"; clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; }; Loading Loading
arch/arm64/boot/dts/qcom/trinket-coresight.dtsi +3 −3 Original line number Diff line number Diff line Loading @@ -2214,7 +2214,7 @@ reg-names = "cti-base"; coresight-name = "coresight-cti-wcss_cti0"; status = "disabled"; clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; }; Loading @@ -2226,7 +2226,7 @@ reg-names = "cti-base"; coresight-name = "coresight-cti-wcss_cti1"; status = "disabled"; clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; }; Loading @@ -2238,7 +2238,7 @@ reg-names = "cti-base"; coresight-name = "coresight-cti-wcss_cti2"; status = "disabled"; clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; }; Loading