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Commit 63d74ae5 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add MHI device tree nodes for sm8150"

parents 09d7f017 b9428952

arch/arm64/boot/dts/qcom/sm8150-cdp.dtsi

+5 −0
Original line number Diff line number Diff line
@@ -381,3 +381,8 @@ 
&wil6210 {

	status = "ok";

};



&mhi_0 {

	mhi,fw-name = "debug.mbn";

	status = "okay";

};

arch/arm64/boot/dts/qcom/sm8150-mtp.dtsi

+5 −0
Original line number Diff line number Diff line
@@ -385,3 +385,8 @@ 
&wil6210 {

	status = "ok";

};



&mhi_0 {

	mhi,fw-name = "debug.mbn";

	status = "okay";

};

arch/arm64/boot/dts/qcom/sm8150-sdx50m.dtsi

+13 −0
Original line number Diff line number Diff line
@@ -38,3 +38,16 @@ 
		};

	};

};



&mhi_0 {

	esoc-names = "mdm";

	esoc-0 = <&mdm3>;

	qcom,smmu-cfg = <0x1d>;

	qcom,addr-win = <0x0 0x20000000 0x0 0x3fffffff>;

	mhi,fw-name = "sdx50m/sbl1.mbn";

	status = "okay";

};



&pcie1 {

	dma-coherent;

};

arch/arm64/boot/dts/qcom/sm8150.dtsi

+71 −0
Original line number Diff line number Diff line
@@ -40,6 +40,9 @@ 
		sdhc2 = &sdhc_2; /* SDC2 SD card slot */

		pci-domain0 = &pcie0; /* PCIe0 domain */

		pci-domain1 = &pcie1; /* PCIe1 domain */

		mhi0 = &mhi_0;

		mhi_netdev0 = &mhi_netdev_0;

		mhi_netdev1 = &mhi_netdev_1;

	};



	aliases {
@@ -3179,6 +3182,74 @@ 
		qcom,smmu-coherent;

		status = "disabled";

	};



	mhi_0: qcom,mhi@0 {

		/* controller specific configuration */

		compatible = "qcom,mhi";

		qcom,pci-domain = <1>;

		qcom,pci-bus = <1>;

		qcom,pci-slot = <0>;

		qcom,smmu-cfg = <0x3>;

		qcom,msm-bus,name = "mhi";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

					<100 512 0 0>,

					<100 512 1200000000 650000000>;



		/* mhi bus specific settings */

		mhi,max-channels = <106>;

		mhi,chan-cfg =

			<0 64 2 1 2 0 2 0 0>, <1 64 2 2 2 0 2 0 0>,

			<2 128 1 1 2 0 1 0 0>, <3 128 1 2 2 0 1 0 0>,

			<4 64 1 1 2 0 2 0 0>, <5 64 3 2 2 0 2 0 0x8>,

			<8 64 1 1 2 0 2 0 0>, <9 64 1 2 2 0 2 0 0>,

			<10 64 1 1 2 0 2 0 0>, <11 64 1 2 2 0 2 0 0>,

			<14 64 1 1 2 0 2 0 0>, <15 64 2 2 2 0 2 0 0>,

			<16 64 3 1 2 0 2 0 0>, <17 64 3 2 2 0 2 0 0>,

			<18 64 1 1 2 0 2 0 0>, <19 64 1 2 2 0 2 0 0>,

			<20 64 2 1 2 0 2 1 0>, <21 64 2 2 2 0 2 0 0x8>,

			<22 64 2 1 2 0 2 0 0>, <23 64 2 2 2 0 2 0 0>,

			<24 64 2 1 2 0 1 0 0>, <25 64 2 2 2 0 1 0 0>,

			<26 64 3 1 2 0 2 0 0>, <27 64 3 2 2 0 2 0 0>,

			<32 64 3 1 2 0 2 0 0>, <33 64 3 2 2 0 2 0 0>,

			<100 512 4 1 3 1 2 1 0x4>, <101 512 5 2 3 1 2 1 0>;

		mhi,chan-names = "LOOPBACK", "LOOPBACK",

				 "SAHARA", "SAHARA",

				 "DIAG", "DIAG",

				 "QDSS", "QDSS",

				 "EFS", "EFS",

				 "QMI0", "QMI0",

				 "QMI1", "QMI1",

				 "IP_CTRL", "IP_CTRL",

				 "IPCR", "IPCR",

				 "TF", "TF",

				 "BL", "BL",

				 "DCI", "DCI",

				 "DUN", "DUN",

				 "IP_HW0", "IP_HW0";

		mhi,ev-cfg = <32 0 1 0 1 2 0x8>,

			     <256 1 2 0 1 2 0>,

			     <256 1 3 0 1 2 0>,

			     <256 1 4 0 1 2 0>,

			     <1024 5 5 100 1 3 0x1>,

			     <1024 5 6 101 1 3 0x3>;

		mhi,timeout = <2000>;

		status = "disabled";



		mhi_netdev_0: mhi_rmnet@0 {

			     mhi,chan = "IP_HW0";

			     mhi,interface-name = "rmnet_mhi";

			     mhi,mru = <0x4000>;

			     mhi,recycle-buf;

		};



		mhi_netdev_1: mhi_rmnet@1 {

			     mhi,chan = "IP_HW_ADPL";

			     mhi,interface-name = "rmnet_mhi";

			     mhi,mru = <0x4000>;

		};

	};

};



&emac_gdsc {