Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 63cfd142 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
Browse files

Merge "drm/msm/dsi-staging: add DSI 7nm PHY and DSI ctrl 2.3 support"

parents 41865882 1f6070ff

Documentation/devicetree/bindings/drm/msm/sde-dsi.txt

+2 −2
Original line number Diff line number Diff line
@@ -8,11 +8,11 @@ Required properties: 
- compatible:           Should be "qcom,dsi-ctrl-hw-v<version>". Supported

			versions include 1.4, 2.0 and 2.2.

			eg: qcom,dsi-ctrl-hw-v1.4, qcom,dsi-ctrl-hw-v2.0,

			qcom,dsi-ctrl-hw-v2.2

			qcom,dsi-ctrl-hw-v2.2, qcom,dsi-ctrl-hw-v2.3

			And for dsi phy driver:

			qcom,dsi-phy-v0.0-hpm, qcom,dsi-phy-v0.0-lpm,

			qcom,dsi-phy-v1.0, qcom,dsi-phy-v2.0,

			qcom,dsi-phy-v3.0

			qcom,dsi-phy-v3.0, qcom,dsi-phy-v4.0

- reg:                  Base address and length of DSI controller's memory

			mapped regions.

- reg-names:            A list of strings that name the list of regs.

drivers/gpu/drm/msm/Makefile

+2 −0
Original line number Diff line number Diff line
@@ -130,9 +130,11 @@ msm_drm-$(CONFIG_DRM_MSM_DSI_STAGING) += dsi-staging/dsi_phy.o \ 
				dsi-staging/dsi_phy.o \

				dsi-staging/dsi_phy_hw_v2_0.o \

				dsi-staging/dsi_phy_hw_v3_0.o \

				dsi-staging/dsi_phy_hw_v4_0.o \

				dsi-staging/dsi_phy_timing_calc.o \

				dsi-staging/dsi_phy_timing_v2_0.o \

				dsi-staging/dsi_phy_timing_v3_0.o \

				dsi-staging/dsi_phy_timing_v4_0.o \

				dsi-staging/dsi_ctrl_hw_cmn.o \

				dsi-staging/dsi_ctrl_hw_1_4.o \

				dsi-staging/dsi_ctrl_hw_2_0.o \

drivers/gpu/drm/msm/dsi-staging/dsi_catalog.c

+31 −1
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.

 * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -101,6 +101,7 @@ static void dsi_catalog_cmn_init(struct dsi_ctrl_hw *ctrl, 
		ctrl->ops.kickoff_command_non_embedded_mode = NULL;

		break;

	case DSI_CTRL_VERSION_2_2:

	case DSI_CTRL_VERSION_2_3:

		ctrl->ops.phy_reset_config = dsi_ctrl_hw_22_phy_reset_config;

		ctrl->ops.get_cont_splash_status =

			dsi_ctrl_hw_22_get_cont_splash_status;
@@ -162,6 +163,7 @@ int dsi_catalog_ctrl_setup(struct dsi_ctrl_hw *ctrl, 
		break;

	case DSI_CTRL_VERSION_2_0:

	case DSI_CTRL_VERSION_2_2:

	case DSI_CTRL_VERSION_2_3:

		ctrl->phy_isolation_enabled = phy_isolation_enabled;

		dsi_catalog_cmn_init(ctrl, version);

		break;
@@ -215,6 +217,31 @@ static void dsi_catalog_phy_3_0_init(struct dsi_phy_hw *phy) 
	phy->ops.phy_lane_reset = dsi_phy_hw_v3_0_lane_reset;

}



/**

 * dsi_catalog_phy_4_0_init() - catalog init for DSI PHY 7nm

 */

static void dsi_catalog_phy_4_0_init(struct dsi_phy_hw *phy)

{

	phy->ops.regulator_enable = NULL;

	phy->ops.regulator_disable = NULL;

	phy->ops.enable = dsi_phy_hw_v4_0_enable;

	phy->ops.disable = dsi_phy_hw_v4_0_disable;

	phy->ops.calculate_timing_params =

		dsi_phy_hw_calculate_timing_params;

	phy->ops.ulps_ops.wait_for_lane_idle =

		dsi_phy_hw_v4_0_wait_for_lane_idle;

	phy->ops.ulps_ops.ulps_request =

		dsi_phy_hw_v4_0_ulps_request;

	phy->ops.ulps_ops.ulps_exit =

		dsi_phy_hw_v4_0_ulps_exit;

	phy->ops.ulps_ops.get_lanes_in_ulps =

		dsi_phy_hw_v4_0_get_lanes_in_ulps;

	phy->ops.ulps_ops.is_lanes_in_ulps =

		dsi_phy_hw_v4_0_is_lanes_in_ulps;

	phy->ops.phy_timing_val = dsi_phy_hw_timing_val_v4_0;

	phy->ops.phy_lane_reset = dsi_phy_hw_v4_0_lane_reset;

}



/**

 * dsi_catalog_phy_setup() - return catalog info for dsi phy hardware

 * @ctrl:        Pointer to DSI PHY hw object.
@@ -249,6 +276,9 @@ int dsi_catalog_phy_setup(struct dsi_phy_hw *phy, 
	case DSI_PHY_VERSION_3_0:

		dsi_catalog_phy_3_0_init(phy);

		break;

	case DSI_PHY_VERSION_4_0:

		dsi_catalog_phy_4_0_init(phy);

		break;

	case DSI_PHY_VERSION_0_0_HPM:

	case DSI_PHY_VERSION_0_0_LPM:

	case DSI_PHY_VERSION_1_0:

drivers/gpu/drm/msm/dsi-staging/dsi_catalog.h

+15 −1
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.

 * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -104,6 +104,20 @@ int dsi_phy_hw_timing_val_v3_0(struct dsi_phy_per_lane_cfgs *timing_cfg, 
		u32 *timing_val, u32 size);

int dsi_phy_hw_v3_0_lane_reset(struct dsi_phy_hw *phy);



/* Definitions for 7nm PHY hardware driver */

void dsi_phy_hw_v4_0_enable(struct dsi_phy_hw *phy, struct dsi_phy_cfg *cfg);

void dsi_phy_hw_v4_0_disable(struct dsi_phy_hw *phy, struct dsi_phy_cfg *cfg);

int dsi_phy_hw_v4_0_wait_for_lane_idle(struct dsi_phy_hw *phy, u32 lanes);

void dsi_phy_hw_v4_0_ulps_request(struct dsi_phy_hw *phy,

		struct dsi_phy_cfg *cfg, u32 lanes);

void dsi_phy_hw_v4_0_ulps_exit(struct dsi_phy_hw *phy,

			struct dsi_phy_cfg *cfg, u32 lanes);

u32 dsi_phy_hw_v4_0_get_lanes_in_ulps(struct dsi_phy_hw *phy);

bool dsi_phy_hw_v4_0_is_lanes_in_ulps(u32 lanes, u32 ulps_lanes);

int dsi_phy_hw_timing_val_v4_0(struct dsi_phy_per_lane_cfgs *timing_cfg,

		u32 *timing_val, u32 size);

int dsi_phy_hw_v4_0_lane_reset(struct dsi_phy_hw *phy);



/* DSI controller common ops */

u32 dsi_ctrl_hw_cmn_get_interrupt_status(struct dsi_ctrl_hw *ctrl);

void dsi_ctrl_hw_cmn_debug_bus(struct dsi_ctrl_hw *ctrl);

drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c

+7 −1
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.

 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -67,6 +67,7 @@ static DEFINE_MUTEX(dsi_ctrl_list_lock); 
static const enum dsi_ctrl_version dsi_ctrl_v1_4 = DSI_CTRL_VERSION_1_4;

static const enum dsi_ctrl_version dsi_ctrl_v2_0 = DSI_CTRL_VERSION_2_0;

static const enum dsi_ctrl_version dsi_ctrl_v2_2 = DSI_CTRL_VERSION_2_2;

static const enum dsi_ctrl_version dsi_ctrl_v2_3 = DSI_CTRL_VERSION_2_3;



static const struct of_device_id msm_dsi_of_match[] = {

	{
@@ -81,6 +82,10 @@ static const struct of_device_id msm_dsi_of_match[] = { 
		.compatible = "qcom,dsi-ctrl-hw-v2.2",

		.data = &dsi_ctrl_v2_2,

	},

	{

		.compatible = "qcom,dsi-ctrl-hw-v2.3",

		.data = &dsi_ctrl_v2_3,

	},

	{}

};
@@ -463,6 +468,7 @@ static int dsi_ctrl_init_regmap(struct platform_device *pdev, 
		ctrl->hw.disp_cc_base = NULL;

		break;

	case DSI_CTRL_VERSION_2_2:

	case DSI_CTRL_VERSION_2_3:

		ptr = msm_ioremap(pdev, "disp_cc_base", ctrl->name);

		if (IS_ERR(ptr)) {

			pr_err("disp_cc base address not found for [%s]\n",