Loading drivers/gpu/drm/msm/dp/dp_panel.c +16 −0 Original line number Diff line number Diff line Loading @@ -1512,12 +1512,14 @@ static int dp_panel_dsc_prepare_basic_params( struct dp_dsc_slices_per_line *rec; int slice_width; u32 ppr = dp_mode->timing.pixel_clk_khz/1000; int max_slice_width; comp_info->dsc_info.slice_per_pkt = 0; for (i = 0; i < ARRAY_SIZE(slice_per_line_tbl); i++) { rec = &slice_per_line_tbl[i]; if ((ppr > rec->min_ppr) && (ppr <= rec->max_ppr)) { comp_info->dsc_info.slice_per_pkt = rec->num_slices; i++; break; } } Loading @@ -1525,9 +1527,21 @@ static int dp_panel_dsc_prepare_basic_params( if (comp_info->dsc_info.slice_per_pkt == 0) return -EINVAL; max_slice_width = dp_panel->dsc_dpcd[12] * 320; slice_width = (dp_mode->timing.h_active / comp_info->dsc_info.slice_per_pkt); while (slice_width >= max_slice_width) { if (i == ARRAY_SIZE(slice_per_line_tbl)) return -EINVAL; rec = &slice_per_line_tbl[i]; comp_info->dsc_info.slice_per_pkt = rec->num_slices; slice_width = (dp_mode->timing.h_active / comp_info->dsc_info.slice_per_pkt); i++; } comp_info->dsc_info.block_pred_enable = dp_panel->sink_dsc_caps.block_pred_en; comp_info->dsc_info.vbr_enable = 0; Loading Loading @@ -2832,6 +2846,8 @@ struct dp_panel *dp_panel_get(struct dp_panel_in *in) if (in->base_panel) { memcpy(dp_panel->dpcd, in->base_panel->dpcd, DP_RECEIVER_CAP_SIZE + 1); memcpy(dp_panel->dsc_dpcd, in->base_panel->dsc_dpcd, DP_RECEIVER_DSC_CAP_SIZE + 1); memcpy(&dp_panel->link_info, &in->base_panel->link_info, sizeof(dp_panel->link_info)); dp_panel->mst_state = in->base_panel->mst_state; Loading drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c +2 −11 Original line number Diff line number Diff line Loading @@ -40,9 +40,6 @@ #define TO_ON_OFF(x) ((x) ? "ON" : "OFF") #define CEIL(x, y) (((x) + ((y)-1)) / (y)) #define TICKS_IN_MICRO_SECOND 1000000 /** * enum dsi_ctrl_driver_ops - controller driver ops */ Loading Loading @@ -833,7 +830,7 @@ static int dsi_ctrl_update_link_freqs(struct dsi_ctrl *dsi_ctrl, { int rc = 0; u32 num_of_lanes = 0; u32 bpp, refresh_rate = TICKS_IN_MICRO_SECOND; u32 bpp; u64 h_period, v_period, bit_rate, pclk_rate, bit_rate_per_lane, byte_clk_rate; struct dsi_host_common_cfg *host_cfg = &config->common_config; Loading @@ -858,13 +855,7 @@ static int dsi_ctrl_update_link_freqs(struct dsi_ctrl *dsi_ctrl, if (config->bit_clk_rate_hz_override == 0) { h_period = DSI_H_TOTAL_DSC(timing); v_period = DSI_V_TOTAL(timing); if (config->panel_mode == DSI_OP_CMD_MODE) do_div(refresh_rate, timing->mdp_transfer_time_us); else refresh_rate = timing->refresh_rate; bit_rate = h_period * v_period * refresh_rate * bpp; bit_rate = h_period * v_period * timing->refresh_rate * bpp; } else { bit_rate = config->bit_clk_rate_hz_override * num_of_lanes; } Loading drivers/gpu/drm/msm/dsi-staging/dsi_display.c +3 −1 Original line number Diff line number Diff line Loading @@ -4702,7 +4702,7 @@ static ssize_t sysfs_dynamic_dsi_clk_read(struct device *dev, static ssize_t sysfs_dynamic_dsi_clk_write(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { int rc = count; int rc = 0; int clk_rate; struct dsi_display *display; Loading Loading @@ -4731,6 +4731,8 @@ static ssize_t sysfs_dynamic_dsi_clk_write(struct device *dev, rc = dsi_display_dynamic_clk_configure_cmd(display, clk_rate); if (rc) pr_err("Failed to configure dynamic clk\n"); else rc = count; mutex_unlock(&dsi_display_clk_mutex); mutex_unlock(&display->display_lock); Loading drivers/gpu/drm/msm/dsi-staging/dsi_panel.c +3 −0 Original line number Diff line number Diff line Loading @@ -3470,6 +3470,9 @@ int dsi_panel_get_mode(struct dsi_panel *panel, goto parse_fail; } if (panel->panel_mode == DSI_OP_VIDEO_MODE) mode->priv_info->mdp_transfer_time_us = 0; rc = dsi_panel_parse_dsc_params(mode, utils); if (rc) { pr_err("failed to parse dsc params, rc=%d\n", rc); Loading drivers/media/platform/msm/sde/rotator/sde_rotator_base.c +26 −7 Original line number Diff line number Diff line Loading @@ -79,6 +79,7 @@ u32 sde_apply_comp_ratio_factor(u32 quota, #define RES_1080p (1088*1920) #define RES_UHD (3840*2160) #define RES_WQXGA (2560*1600) #define XIN_HALT_TIMEOUT_US 0x4000 static int sde_mdp_wait_for_xin_halt(u32 xin_id) Loading Loading @@ -242,18 +243,36 @@ u32 sde_mdp_get_ot_limit(u32 width, u32 height, u32 pixfmt, u32 fps, u32 is_rd) SDEROT_DBG("w:%d h:%d fps:%d pixfmt:%8.8x yuv:%d res:%llu rd:%d\n", width, height, fps, pixfmt, is_yuv, res, is_rd); if (!is_yuv) goto exit; /* * If (total_source_pixels <= 62208000 && YUV) -> RD/WROT=2 //1080p30 * If (total_source_pixels <= 124416000 && YUV) -> RD/WROT=4 //1080p60 * If (total_source_pixels <= 2160p && YUV && FPS <= 30) -> RD/WROT = 32 */ switch (mdata->mdss_version) { case SDE_MDP_HW_REV_540: if (is_yuv) { if (res <= (RES_1080p * 30)) ot_lim = 2; else if (res <= (RES_1080p * 60)) ot_lim = 4; else if (res <= (RES_WQXGA * 60)) ot_lim = 4; else if (res <= (RES_UHD * 30)) ot_lim = 8; } else if (fmt->bpp == 4 && res <= (RES_WQXGA * 60)) { ot_lim = 16; } break; default: if (is_yuv) { if (res <= (RES_1080p * 30)) ot_lim = 2; else if (res <= (RES_1080p * 60)) ot_lim = 4; } break; } exit: SDEROT_DBG("ot_lim=%d\n", ot_lim); Loading Loading
drivers/gpu/drm/msm/dp/dp_panel.c +16 −0 Original line number Diff line number Diff line Loading @@ -1512,12 +1512,14 @@ static int dp_panel_dsc_prepare_basic_params( struct dp_dsc_slices_per_line *rec; int slice_width; u32 ppr = dp_mode->timing.pixel_clk_khz/1000; int max_slice_width; comp_info->dsc_info.slice_per_pkt = 0; for (i = 0; i < ARRAY_SIZE(slice_per_line_tbl); i++) { rec = &slice_per_line_tbl[i]; if ((ppr > rec->min_ppr) && (ppr <= rec->max_ppr)) { comp_info->dsc_info.slice_per_pkt = rec->num_slices; i++; break; } } Loading @@ -1525,9 +1527,21 @@ static int dp_panel_dsc_prepare_basic_params( if (comp_info->dsc_info.slice_per_pkt == 0) return -EINVAL; max_slice_width = dp_panel->dsc_dpcd[12] * 320; slice_width = (dp_mode->timing.h_active / comp_info->dsc_info.slice_per_pkt); while (slice_width >= max_slice_width) { if (i == ARRAY_SIZE(slice_per_line_tbl)) return -EINVAL; rec = &slice_per_line_tbl[i]; comp_info->dsc_info.slice_per_pkt = rec->num_slices; slice_width = (dp_mode->timing.h_active / comp_info->dsc_info.slice_per_pkt); i++; } comp_info->dsc_info.block_pred_enable = dp_panel->sink_dsc_caps.block_pred_en; comp_info->dsc_info.vbr_enable = 0; Loading Loading @@ -2832,6 +2846,8 @@ struct dp_panel *dp_panel_get(struct dp_panel_in *in) if (in->base_panel) { memcpy(dp_panel->dpcd, in->base_panel->dpcd, DP_RECEIVER_CAP_SIZE + 1); memcpy(dp_panel->dsc_dpcd, in->base_panel->dsc_dpcd, DP_RECEIVER_DSC_CAP_SIZE + 1); memcpy(&dp_panel->link_info, &in->base_panel->link_info, sizeof(dp_panel->link_info)); dp_panel->mst_state = in->base_panel->mst_state; Loading
drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c +2 −11 Original line number Diff line number Diff line Loading @@ -40,9 +40,6 @@ #define TO_ON_OFF(x) ((x) ? "ON" : "OFF") #define CEIL(x, y) (((x) + ((y)-1)) / (y)) #define TICKS_IN_MICRO_SECOND 1000000 /** * enum dsi_ctrl_driver_ops - controller driver ops */ Loading Loading @@ -833,7 +830,7 @@ static int dsi_ctrl_update_link_freqs(struct dsi_ctrl *dsi_ctrl, { int rc = 0; u32 num_of_lanes = 0; u32 bpp, refresh_rate = TICKS_IN_MICRO_SECOND; u32 bpp; u64 h_period, v_period, bit_rate, pclk_rate, bit_rate_per_lane, byte_clk_rate; struct dsi_host_common_cfg *host_cfg = &config->common_config; Loading @@ -858,13 +855,7 @@ static int dsi_ctrl_update_link_freqs(struct dsi_ctrl *dsi_ctrl, if (config->bit_clk_rate_hz_override == 0) { h_period = DSI_H_TOTAL_DSC(timing); v_period = DSI_V_TOTAL(timing); if (config->panel_mode == DSI_OP_CMD_MODE) do_div(refresh_rate, timing->mdp_transfer_time_us); else refresh_rate = timing->refresh_rate; bit_rate = h_period * v_period * refresh_rate * bpp; bit_rate = h_period * v_period * timing->refresh_rate * bpp; } else { bit_rate = config->bit_clk_rate_hz_override * num_of_lanes; } Loading
drivers/gpu/drm/msm/dsi-staging/dsi_display.c +3 −1 Original line number Diff line number Diff line Loading @@ -4702,7 +4702,7 @@ static ssize_t sysfs_dynamic_dsi_clk_read(struct device *dev, static ssize_t sysfs_dynamic_dsi_clk_write(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { int rc = count; int rc = 0; int clk_rate; struct dsi_display *display; Loading Loading @@ -4731,6 +4731,8 @@ static ssize_t sysfs_dynamic_dsi_clk_write(struct device *dev, rc = dsi_display_dynamic_clk_configure_cmd(display, clk_rate); if (rc) pr_err("Failed to configure dynamic clk\n"); else rc = count; mutex_unlock(&dsi_display_clk_mutex); mutex_unlock(&display->display_lock); Loading
drivers/gpu/drm/msm/dsi-staging/dsi_panel.c +3 −0 Original line number Diff line number Diff line Loading @@ -3470,6 +3470,9 @@ int dsi_panel_get_mode(struct dsi_panel *panel, goto parse_fail; } if (panel->panel_mode == DSI_OP_VIDEO_MODE) mode->priv_info->mdp_transfer_time_us = 0; rc = dsi_panel_parse_dsc_params(mode, utils); if (rc) { pr_err("failed to parse dsc params, rc=%d\n", rc); Loading
drivers/media/platform/msm/sde/rotator/sde_rotator_base.c +26 −7 Original line number Diff line number Diff line Loading @@ -79,6 +79,7 @@ u32 sde_apply_comp_ratio_factor(u32 quota, #define RES_1080p (1088*1920) #define RES_UHD (3840*2160) #define RES_WQXGA (2560*1600) #define XIN_HALT_TIMEOUT_US 0x4000 static int sde_mdp_wait_for_xin_halt(u32 xin_id) Loading Loading @@ -242,18 +243,36 @@ u32 sde_mdp_get_ot_limit(u32 width, u32 height, u32 pixfmt, u32 fps, u32 is_rd) SDEROT_DBG("w:%d h:%d fps:%d pixfmt:%8.8x yuv:%d res:%llu rd:%d\n", width, height, fps, pixfmt, is_yuv, res, is_rd); if (!is_yuv) goto exit; /* * If (total_source_pixels <= 62208000 && YUV) -> RD/WROT=2 //1080p30 * If (total_source_pixels <= 124416000 && YUV) -> RD/WROT=4 //1080p60 * If (total_source_pixels <= 2160p && YUV && FPS <= 30) -> RD/WROT = 32 */ switch (mdata->mdss_version) { case SDE_MDP_HW_REV_540: if (is_yuv) { if (res <= (RES_1080p * 30)) ot_lim = 2; else if (res <= (RES_1080p * 60)) ot_lim = 4; else if (res <= (RES_WQXGA * 60)) ot_lim = 4; else if (res <= (RES_UHD * 30)) ot_lim = 8; } else if (fmt->bpp == 4 && res <= (RES_WQXGA * 60)) { ot_lim = 16; } break; default: if (is_yuv) { if (res <= (RES_1080p * 30)) ot_lim = 2; else if (res <= (RES_1080p * 60)) ot_lim = 4; } break; } exit: SDEROT_DBG("ot_lim=%d\n", ot_lim); Loading