coretech: Import latest OnePlus changes (638a815f) · Commits · e / devices / android_kernel_oneplus_sm8150

coretech/control_center/control_center.c

+148 −109

Original line number	Diff line number	Diff line
		@@ -43,20 +43,20 @@ module_param_named(time_measure, cc_time_measure, bool, 0644);
		static bool cc_cpu_boost_enable = true;
		module_param_named(cpu_boost_enable, cc_cpu_boost_enable, bool, 0644);

		static bool cc_ddr_boost_enable = true;
		bool cc_ddr_boost_enable = true;
		module_param_named(ddr_boost_enable, cc_ddr_boost_enable, bool, 0644);

		bool cc_ddr_lower_bound_enable = false;
		module_param_named(ddr_lower_bound_enable, cc_ddr_lower_bound_enable, bool, 0644);

		bool cc_ddr_set_enable = false;
		module_param_named(ddr_set_enable, cc_ddr_set_enable, bool, 0644);

		/* FIXME
		* this is for voting, should not named as lock_
		*/
		bool cc_ddr_lock_enable = true;
		module_param_named(ddr_lock_enable, cc_ddr_lock_enable, bool, 0644);
		//bool cc_ddr_lower_bound_enable = false;
		//module_param_named(ddr_lower_bound_enable, cc_ddr_lower_bound_enable, bool, 0644);
		//
		//bool cc_ddr_set_enable = false;
		//module_param_named(ddr_set_enable, cc_ddr_set_enable, bool, 0644);
		//
		///* FIXME
		// * this is for voting, should not named as lock_
		// */
		//bool cc_ddr_lock_enable = true;
		//module_param_named(ddr_lock_enable, cc_ddr_lock_enable, bool, 0644);

		/* record */
		static struct cc_record {
		@@ -377,74 +377,78 @@ static inline u64 cc_ddr_to_devfreq(u64 val)
		u64 ddr_aop_mapping_freq[] = { 0, 681, 768, 1017, 1353, 1555, 1804, 2092 };

		/* map to devfreq whlie config is enabled */
		if (cc_ddr_set_enable \|\| cc_ddr_lock_enable) {
		//if (cc_ddr_set_enable \|\| cc_ddr_lock_enable) {
		// for (i = ARRAY_SIZE(ddr_devfreq_avail_freq) - 1; i >= 0; --i) {
		// if (val >= ddr_aop_mapping_freq[i])
		// return ddr_devfreq_avail_freq[i];
		// }
		//}
		for (i = ARRAY_SIZE(ddr_devfreq_avail_freq) - 1; i >= 0; --i) {
		if (val >= ddr_aop_mapping_freq[i])
		return ddr_devfreq_avail_freq[i];
		}
		}
		return val;
		}

		u64 cc_cpu_find_ddr(int cpu)
		{
		int i, len, idx = 0;
		u64 ddr, curr;
		struct cpufreq_policy *pol;
		u64 tmp_cpu, tmp_ddr;
		u64 *ddr_cluster0_options;
		u64 *ddr_cluster1_options;

		u64 ddr_cluster0_vote_options[5] = {
		762, 1720, 2086, 2929, 3879
		};
		u64 ddr_cluster1_vote_options[9] = {
		762, 1720, 2086, 2929, 3879, 5161, 5931, 6881, 7980
		};
		u64 ddr_cluster0_lock_options[5] = {
		200, 451, 547, 768, 1017
		};
		u64 ddr_cluster1_lock_options[9] = {
		200, 451, 547, 768, 1017, 1353, 1555, 1804, 2092
		};
		u64 cpu_cluster0_options[5] = {
		300000, 768000, 1113600, 1478400, 1632000
		};
		u64 cpu_cluster1_options[9] = {
		300000, 710400, 825600, 1056000, 1286400, 1612800, 1804800, 2649600, 3000000
		};

		if (cc_ddr_set_enable \|\| cc_ddr_lock_enable) {
		ddr_cluster0_options = ddr_cluster0_vote_options;
		ddr_cluster1_options = ddr_cluster1_vote_options;
		} else {
		ddr_cluster0_options = ddr_cluster0_lock_options;
		ddr_cluster1_options = ddr_cluster1_lock_options;
		}

		pol = cpufreq_cpu_get(cpu);
		if (unlikely(!pol))
		return 0;
		idx = (cpu > 3) ? 1 : 0;
		curr = pol->cur;
		if (idx) {
		tmp_cpu = cpu_cluster1_options;
		tmp_ddr = ddr_cluster1_options;
		len = ARRAY_SIZE(cpu_cluster1_options);
		} else {
		tmp_cpu = cpu_cluster0_options;
		tmp_ddr = ddr_cluster0_options;
		len = ARRAY_SIZE(cpu_cluster0_options);
		}
		for (i = len - 1; i >= 0; --i) {
		if (curr > tmp_cpu[i]) {
		ddr = tmp_ddr[min(i+1, len - 1)];
		break;
		}
		}
		cpufreq_cpu_put(pol);
		return ddr;
		}
		//u64 cc_cpu_find_ddr(int cpu)
		//{
		// int i, len, idx = 0;
		// u64 ddr, curr;
		// struct cpufreq_policy *pol;
		// u64 tmp_cpu, tmp_ddr;
		// u64 *ddr_cluster0_options;
		// u64 *ddr_cluster1_options;
		//
		// u64 ddr_cluster0_vote_options[5] = {
		// 762, 1720, 2086, 2929, 3879
		// };
		// u64 ddr_cluster1_vote_options[9] = {
		// 762, 1720, 2086, 2929, 3879, 5161, 5931, 6881, 7980
		// };
		// u64 ddr_cluster0_lock_options[5] = {
		// 200, 451, 547, 768, 1017
		// };
		// u64 ddr_cluster1_lock_options[9] = {
		// 200, 451, 547, 768, 1017, 1353, 1555, 1804, 2092
		// };
		// u64 cpu_cluster0_options[5] = {
		// 300000, 768000, 1113600, 1478400, 1632000
		// };
		// u64 cpu_cluster1_options[9] = {
		// 300000, 710400, 825600, 1056000, 1286400, 1612800, 1804800, 2649600, 3000000
		// };
		//
		// if (cc_ddr_set_enable \|\| cc_ddr_lock_enable) {
		// ddr_cluster0_options = ddr_cluster0_vote_options;
		// ddr_cluster1_options = ddr_cluster1_vote_options;
		// } else {
		// ddr_cluster0_options = ddr_cluster0_lock_options;
		// ddr_cluster1_options = ddr_cluster1_lock_options;
		// }
		//
		// pol = cpufreq_cpu_get(cpu);
		// if (unlikely(!pol))
		// return 0;
		// idx = (cpu > 3) ? 1 : 0;
		// curr = pol->cur;
		// if (idx) {
		// tmp_cpu = cpu_cluster1_options;
		// tmp_ddr = ddr_cluster1_options;
		// len = ARRAY_SIZE(cpu_cluster1_options);
		// } else {
		// tmp_cpu = cpu_cluster0_options;
		// tmp_ddr = ddr_cluster0_options;
		// len = ARRAY_SIZE(cpu_cluster0_options);
		// }
		// for (i = len - 1; i >= 0; --i) {
		// if (curr > tmp_cpu[i]) {
		// ddr = tmp_ddr[min(i+1, len - 1)];
		// break;
		// }
		// }
		// cpufreq_cpu_put(pol);
		// return ddr;
		//}

		static void cc_adjust_cpufreq_boost(struct cc_command* cc)
		{
		@@ -548,45 +552,73 @@ static void cc_query_ddrfreq(struct cc_command* cc)
		}

		atomic_t cc_expect_ddrfreq;

		static void cc_adjust_ddr_freq(struct cc_command *cc)
		{
		#define CC_DDR_RESET_VAL 0
		//static void cc_adjust_ddr_freq(struct cc_command *cc)
		//{
		// u64 val = cc->params[0];
		// u64 cur;
		//
		// if (!cc_ddr_boost_enable)
		// return;
		//
		// val = cc_ddr_to_devfreq(val);
		//
		// if (cc_is_nonblock(cc))
		// return;
		//
		// if (cc_ddr_lower_bound_enable) {
		// val = max(cc_cpu_find_ddr(0), val);
		// val = max(cc_cpu_find_ddr(4), val);
		// }
		//
		// if (cc->type == CC_CTL_TYPE_RESET)
		// val = CC_DDR_RESET_VAL;
		//
		// /* FIXME
		// * check cur & val not guarantee ddrfreq is locked or not */
		// if (cc_ddr_set_enable \|\| cc_ddr_lock_enable) {
		// atomic_set(&cc_expect_ddrfreq, val);
		// } else {
		// /* check if need update */
		// cur = query_ddrfreq();
		//
		// if (cur != val)
		// aop_lock_ddr_freq(val);
		// }
		//}

		static void cc_adjust_ddr_voting_freq(struct cc_command *cc)
		{
		u64 val = cc->params[0];
		u64 cur;

		if (!cc_ddr_boost_enable)
		return;

		#ifdef CONFIG_AIGOV
		if (aigov_hooked()) {
		if (cc->type == CC_CTL_TYPE_RESET \|\|
		cc->type == CC_CTL_TYPE_RESET_NONBLOCK)
		aigov_set_ddrfreq(0);
		else
		aigov_set_ddrfreq(cc->params[0]);
		if (cc_is_nonblock(cc))
		return;
		}
		#endif

		val = cc_ddr_to_devfreq(val);

		if (cc_is_nonblock(cc))
		return;
		if (cc->type == CC_CTL_TYPE_RESET)
		val = CC_DDR_RESET_VAL;

		if (cc_ddr_lower_bound_enable) {
		val = max(cc_cpu_find_ddr(0), val);
		val = max(cc_cpu_find_ddr(4), val);
		atomic_set(&cc_expect_ddrfreq, val);
		}

		static void cc_adjust_ddr_lock_freq(struct cc_command *cc)
		{
		u64 val = cc->params[0];
		u64 cur;

		if (!cc_ddr_boost_enable)
		return;

		if (cc_is_nonblock(cc))
		return;

		if (cc->type == CC_CTL_TYPE_RESET)
		val = CC_DDR_RESET_VAL;

		/* FIXME
		* check cur & val not guarantee ddrfreq is locked or not */
		if (cc_ddr_set_enable \|\| cc_ddr_lock_enable) {
		atomic_set(&cc_expect_ddrfreq, val);
		} else {
		/* check if need update */
		cur = query_ddrfreq();

		@@ -594,8 +626,6 @@ static void cc_adjust_ddr_freq(struct cc_command *cc)
		aop_lock_ddr_freq(val);
		}

		}

		static void cc_adjust_sched(struct cc_command *cc)
		{
		struct task_struct *task = NULL;
		@@ -644,9 +674,13 @@ void cc_process(struct cc_command* cc)
		cc_logv("cpufreq_boost: type: %u, cluster: %llu target: %llu\n", cc->type, cc->params[0], cc->params[1]);
		cc_adjust_cpufreq_boost(cc);
		break;
		case CC_CTL_CATEGORY_DDR_FREQ:
		cc_logv("ddrfreq: type: %u, target: %llu\n", cc->type, cc->params[0]);
		cc_adjust_ddr_freq(cc);
		case CC_CTL_CATEGORY_DDR_VOTING_FREQ:
		cc_logv("ddrfreq voting: type: %u, target: %llu\n", cc->type, cc->params[0]);
		cc_adjust_ddr_voting_freq(cc);
		break;
		case CC_CTL_CATEGORY_DDR_LOCK_FREQ:
		cc_logv("ddrfreq lock: type: %u, target: %llu\n", cc->type, cc->params[0]);
		cc_adjust_ddr_lock_freq(cc);
		break;
		case CC_CTL_CATEGORY_SCHED_PRIME_BOOST:
		cc_logv("sched prime boost: type: %u, param: %llu\n", cc->type, cc->params[0]);
		@@ -1337,7 +1371,12 @@ static int cc_dump_record_show(char buf, const struct kernel_param kp)
		case CC_CTL_CATEGORY_CLUS_1_FREQ: tag = "cpufreq_1:"; break;
		case CC_CTL_CATEGORY_CLUS_2_FREQ: tag = "cpufreq_2:"; break;
		case CC_CTL_CATEGORY_CPU_FREQ_BOOST: tag = "cpufreq_boost:"; break;
		case CC_CTL_CATEGORY_DDR_FREQ: tag = "ddrfreq:"; break;
		case CC_CTL_CATEGORY_DDR_VOTING_FREQ:
		tag = "ddrfreq voting:";
		break;
		case CC_CTL_CATEGORY_DDR_LOCK_FREQ:
		tag = "ddrfreq lock:";
		break;
		case CC_CTL_CATEGORY_SCHED_PRIME_BOOST: tag = "sched_prime_boost:"; break;
		case CC_CTL_CATEGORY_CLUS_0_FREQ_QUERY: tag = "cpufreq_0_query:"; break;
		case CC_CTL_CATEGORY_CLUS_1_FREQ_QUERY: tag = "cpufreq_1_query:"; break;

coretech/houston/houston.c

+85 −34

Original line number	Diff line number	Diff line
		@@ -19,6 +19,7 @@
		#include <linux/cdev.h>
		#include <linux/workqueue.h>
		#include <linux/clk.h>
		#include <linux/jiffies.h>

		#ifdef CONFIG_AIGOV
		#include <linux/oem/aigov.h>
		@@ -113,6 +114,9 @@ static struct list_head ht_rtg_head = LIST_HEAD_INIT(ht_rtg_head);
		*/
		static struct list_head ht_rtg_perf_head = LIST_HEAD_INIT(ht_rtg_perf_head);

		/* report skin_temp to ais */
		static unsigned int thermal_update_period_hz = 100;
		module_param_named(thermal_update_period_hz, thermal_update_period_hz, uint, 0664);

		/*
		* filter mechanism
		@@ -162,6 +166,15 @@ module_param_named(bat_update_period_us, bat_update_period_us, ulong, 0664);

		extern void bq27541_force_update_current(void);

		/* ioctl retry count */
		#define HT_IOCTL_RETRY_MAX 128
		static int ht_ioctl_retry_count = 0;
		module_param_named(ioctl_retry_count, ht_ioctl_retry_count, int, 0664);

		/* brain status */
		static bool ht_brain_active = true;
		module_param_named(brain_active, ht_brain_active, bool, 0664);

		/* fps boost switch */
		static bool fps_boost_enable = true;
		module_param_named(fps_boost_enable, fps_boost_enable, bool, 0664);
		@@ -452,6 +465,29 @@ static void enable_cpu_counters(void* data)
		ht_logi("CPU:%d enable counter\n", smp_processor_id());
		}

		static unsigned int ht_get_temp_delay(int idx)
		{
		static unsigned long next[HT_MONITOR_SIZE] = {0};
		static unsigned int temps[HT_MONITOR_SIZE] = {0};

		/* only allow for reading sensor data */
		if (unlikely(idx < HT_CPU_0 \|\| idx > HT_THERM_1))
		return 0;

		/* update */
		if (jiffies > next[idx] && jiffies - next[idx] > thermal_update_period_hz) {
		next[idx] = jiffies;
		temps[idx] = ht_get_temp(idx);
		}

		if (jiffies < next[idx]) {
		next[idx] = jiffies;
		temps[idx] = ht_get_temp(idx);
		}

		return temps[idx];
		}

		/*
		* boost cpufreq while no ais activated
		* boost_target[0] : pid
		@@ -712,6 +748,7 @@ void ht_collect_perf_data(struct work_struct *work)
		}

		/* notify ai_scheduler that data collected */
		if (likely(ht_brain_active))
		wake_up(&ht_perf_waitq);
		put_task_struct(task);
		}
		@@ -857,7 +894,7 @@ static void do_fps_boost(unsigned int val, unsigned int period_us)
		struct task_struct *t;
		u64 prev_ddr_target = 100;
		u64 ddr_target = 100; /* default value */
		struct cc_command cc;
		//struct cc_command cc;

		if (!fps_boost_enable)
		return;
		@@ -939,38 +976,38 @@ static void do_fps_boost(unsigned int val, unsigned int period_us)
		do_cpufreq_boost_helper(CLUS_2_IDX, val, period_us, orig, cur);
		}

		/* boost ddrfreq */
		if (ais_active) {
		/* setup boost command */
		cc.pid = current->pid;
		cc.prio = CC_PRIO_HIGH;
		cc.period_us = period_us;
		cc.group = CC_CTL_GROUP_GRAPHIC;
		cc.category = CC_CTL_CATEGORY_DDR_FREQ;
		cc.response = 0;
		cc.leader = current->tgid;
		cc.bind_leader = true;
		cc.status = 0;
		cc.type = CC_CTL_TYPE_ONESHOT_NONBLOCK;

		if (val > 0) {
		clk_get_ddr_freq(&prev_ddr_target);
		ddr_target = prev_ddr_target;
		ddr_target /= 1000000;
		ddr_target *= 2;
		ddr_target = ddr_find_target(ddr_target);
		prev_ddr_target = ddr_find_target(prev_ddr_target/1000000);
		if (ddrfreq_hispeed_enable && ddrfreq_hispeed > ddr_target) {
		ht_logv("boost ddr hispeed from %u to %u\n", ddr_target, ddrfreq_hispeed);
		ddr_target = ddrfreq_hispeed;
		}
		cc.params[0] = ddr_target;
		cc_tsk_process(&cc);
		} else {
		cc.type = CC_CTL_TYPE_RESET_NONBLOCK;
		cc_tsk_process(&cc);
		}
		}
		///* boost ddrfreq */
		//if (ais_active) {
		// /* setup boost command */
		// cc.pid = current->pid;
		// cc.prio = CC_PRIO_HIGH;
		// cc.period_us = period_us;
		// cc.group = CC_CTL_GROUP_GRAPHIC;
		// cc.category = CC_CTL_CATEGORY_DDR_FREQ;
		// cc.response = 0;
		// cc.leader = current->tgid;
		// cc.bind_leader = true;
		// cc.status = 0;
		// cc.type = CC_CTL_TYPE_ONESHOT_NONBLOCK;

		// if (val > 0) {
		// clk_get_ddr_freq(&prev_ddr_target);
		// ddr_target = prev_ddr_target;
		// ddr_target /= 1000000;
		// ddr_target *= 2;
		// ddr_target = ddr_find_target(ddr_target);
		// prev_ddr_target = ddr_find_target(prev_ddr_target/1000000);
		// if (ddrfreq_hispeed_enable && ddrfreq_hispeed > ddr_target) {
		// ht_logv("boost ddr hispeed from %u to %u\n", ddr_target, ddrfreq_hispeed);
		// ddr_target = ddrfreq_hispeed;
		// }
		// cc.params[0] = ddr_target;
		// cc_tsk_process(&cc);
		// } else {
		// cc.type = CC_CTL_TYPE_RESET_NONBLOCK;
		// cc_tsk_process(&cc);
		// }
		//}

		if (val > 0) {
		for (i = 0; i < HT_CLUSTERS; ++i) {
		@@ -1306,6 +1343,7 @@ static void ht_collect_system_data(struct ai_parcel *p)
		p->boost_cnt = atomic_read(&boost_cnt);
		p->notify_start_ts_us = p->queued_ts_us;
		p->notify_end_ts_us = ktime_to_us(ktime_get());
		p->skin_temp = ht_get_temp_delay(HT_THERM_0);
		}

		static inline void ht_cpuload_helper(int clus, int cpus, struct cpuload_info *cli)
		@@ -1349,6 +1387,8 @@ static long ht_ctl_ioctl(struct file *file, unsigned int cmd, unsigned long __us
		schedule();
		finish_wait(&ht_perf_waitq, &wait);
		ht_collect_system_data(&parcel);
		ht_ioctl_retry_count = 0;
		ht_brain_active = true;
		if (copy_to_user((struct ai_parcel __user *) arg, &parcel, sizeof(parcel)))
		return 0;
		break;
		@@ -1444,6 +1484,17 @@ static long ht_ctl_ioctl(struct file *file, unsigned int cmd, unsigned long __us
		return 0;
		break;
		}
		default:
		++ht_ioctl_retry_count;
		if (ht_ioctl_retry_count >= HT_IOCTL_RETRY_MAX) {
		DEFINE_WAIT(wait);
		ht_logw("disable support from ai brain\n");
		/* block ai observer here */
		ht_brain_active = false;
		prepare_to_wait(&ht_perf_waitq, &wait, TASK_INTERRUPTIBLE);
		schedule();
		finish_wait(&ht_perf_waitq, &wait);
		}
		}
		return 0;
		}

include/linux/oem/control_center.h

+2 −1

Original line number	Diff line number	Diff line
		@@ -55,7 +55,8 @@ enum CC_CTL_CATEGORY {
		CC_CTL_CATEGORY_CLUS_1_FREQ,
		CC_CTL_CATEGORY_CLUS_2_FREQ,
		CC_CTL_CATEGORY_CPU_FREQ_BOOST,
		CC_CTL_CATEGORY_DDR_FREQ,
		CC_CTL_CATEGORY_DDR_VOTING_FREQ,
		CC_CTL_CATEGORY_DDR_LOCK_FREQ,
		CC_CTL_CATEGORY_SCHED_PRIME_BOOST,

		/* TODO move out from control part */

include/linux/oem/houston.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -181,6 +181,7 @@ struct ai_parcel {
		u64 notify_start_ts_us;
		u64 notify_end_ts_us;
		u64 utils[8];
		u32 skin_temp;
		#ifdef CONFIG_CONTROL_CENTER
		struct cc_boost_ts cbt[CC_BOOST_TS_SIZE];
		#endif