Loading arch/arm64/boot/dts/qcom/sdxprairie-coresight.dtsi +16 −0 Original line number Diff line number Diff line Loading @@ -1158,6 +1158,22 @@ }; ipcb_tgu: tgu@6b0c000 { compatible = "arm,primecell"; arm,primecell-periphid = <0x000bb999>; reg = <0x06b0c000 0x1000>; reg-names = "tgu-base"; tgu-steps = <3>; tgu-conditions = <4>; tgu-regs = <4>; tgu-timer-counters = <8>; coresight-name = "coresight-tgu-ipcb"; clocks = <&clock_aop QDSS_CLK>; clock-names = "apb_pclk"; }; cti0_swao:cti@6b04000 { compatible = "arm,primecell"; arm,primecell-periphid = <0x0003b966>; Loading Loading
arch/arm64/boot/dts/qcom/sdxprairie-coresight.dtsi +16 −0 Original line number Diff line number Diff line Loading @@ -1158,6 +1158,22 @@ }; ipcb_tgu: tgu@6b0c000 { compatible = "arm,primecell"; arm,primecell-periphid = <0x000bb999>; reg = <0x06b0c000 0x1000>; reg-names = "tgu-base"; tgu-steps = <3>; tgu-conditions = <4>; tgu-regs = <4>; tgu-timer-counters = <8>; coresight-name = "coresight-tgu-ipcb"; clocks = <&clock_aop QDSS_CLK>; clock-names = "apb_pclk"; }; cti0_swao:cti@6b04000 { compatible = "arm,primecell"; arm,primecell-periphid = <0x0003b966>; Loading