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Commit 63261d76 authored by Olof Johansson's avatar Olof Johansson
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Merge tag 'omap-for-v3.15/crossbar-signed' of...

Merge tag 'omap-for-v3.15/crossbar-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/drivers

Merge OMAP crossbar support from Tony Lindgren:

Add support for GIC crossbar that routes interrupts on newer omaps.

Looks like people wanted these merged via the omap tree as it's
the only user for the GIC crossbar.

* tag 'omap-for-v3.15/crossbar-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap

:
  ARM: DRA: Enable Crossbar IP support for DRA7XX
  ARM: OMAP4+: Correct Wakeup-gen code to use physical irq number
  DRIVERS: IRQCHIP: CROSSBAR: Add support for Crossbar IP
  DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents c37abe5a 95942742
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+6 −0
Original line number Diff line number Diff line
@@ -50,6 +50,11 @@ Optional
  regions, used when the GIC doesn't have banked registers. The offset is
  cpu-offset * cpu-nr.

- arm,routable-irqs : Total number of gic irq inputs which are not directly
		  connected from the peripherals, but are routed dynamically
		  by a crossbar/multiplexer preceding the GIC. The GIC irq
		  input line is assigned dynamically when the corresponding
		  peripheral's crossbar line is mapped.
Example:

	intc: interrupt-controller@fff11000 {
@@ -57,6 +62,7 @@ Example:
		#interrupt-cells = <3>;
		#address-cells = <1>;
		interrupt-controller;
		arm,routable-irqs = <160>;
		reg = <0xfff11000 0x1000>,
		      <0xfff10100 0x100>;
	};
+27 −0
Original line number Diff line number Diff line
Some socs have a large number of interrupts requests to service
the needs of its many peripherals and subsystems. All of the
interrupt lines from the subsystems are not needed at the same
time, so they have to be muxed to the irq-controller appropriately.
In such places a interrupt controllers are preceded by an CROSSBAR
that provides flexibility in muxing the device requests to the controller
inputs.

Required properties:
- compatible : Should be "ti,irq-crossbar"
- reg: Base address and the size of the crossbar registers.
- ti,max-irqs: Total number of irqs available at the interrupt controller.
- ti,reg-size: Size of a individual register in bytes. Every individual
	    register is assumed to be of same size. Valid sizes are 1, 2, 4.
- ti,irqs-reserved: List of the reserved irq lines that are not muxed using
		 crossbar. These interrupt lines are reserved in the soc,
		 so crossbar bar driver should not consider them as free
		 lines.

Examples:
		crossbar_mpu: @4a020000 {
			compatible = "ti,irq-crossbar";
			reg = <0x4a002a48 0x130>;
			ti,max-irqs = <160>;
			ti,reg-size = <2>;
			ti,irqs-reserved = <0 1 2 3 5 6 131 132 139 140>;
		};
+1 −0
Original line number Diff line number Diff line
@@ -85,6 +85,7 @@ config SOC_DRA7XX
	select CPU_V7
	select HAVE_SMP
	select HAVE_ARM_ARCH_TIMER
	select IRQ_CROSSBAR

config ARCH_OMAP2PLUS
	bool
+2 −2
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@@ -138,7 +138,7 @@ static void wakeupgen_mask(struct irq_data *d)
	unsigned long flags;

	raw_spin_lock_irqsave(&wakeupgen_lock, flags);
	_wakeupgen_clear(d->irq, irq_target_cpu[d->irq]);
	_wakeupgen_clear(d->hwirq, irq_target_cpu[d->hwirq]);
	raw_spin_unlock_irqrestore(&wakeupgen_lock, flags);
}

@@ -150,7 +150,7 @@ static void wakeupgen_unmask(struct irq_data *d)
	unsigned long flags;

	raw_spin_lock_irqsave(&wakeupgen_lock, flags);
	_wakeupgen_set(d->irq, irq_target_cpu[d->irq]);
	_wakeupgen_set(d->hwirq, irq_target_cpu[d->hwirq]);
	raw_spin_unlock_irqrestore(&wakeupgen_lock, flags);
}

+4 −0
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@
#include <linux/of_platform.h>
#include <linux/export.h>
#include <linux/irqchip/arm-gic.h>
#include <linux/irqchip/irq-crossbar.h>
#include <linux/of_address.h>
#include <linux/reboot.h>

@@ -288,5 +289,8 @@ void __init omap_gic_of_init(void)

skip_errata_init:
	omap_wakeupgen_init();
#ifdef CONFIG_IRQ_CROSSBAR
	irqcrossbar_init();
#endif
	irqchip_init();
}
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