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Commit 630171d4 authored by Andi Kleen's avatar Andi Kleen Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events: Add core event list for Skylake Server 



Based on JSON list version v1.01

Signed-off-by: default avatarAndi Kleen <ak@linux.intel.com>
Link: http://lkml.kernel.org/r/3269ae458a883139110ec82bc895423bd8843d65


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent d66dccdb

tools/perf/pmu-events/arch/x86/mapfile.csv

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@@ -34,3 +34,4 @@ GenuineIntel-6-2C,v2,westmereep-dp,core 
GenuineIntel-6-2C,v2,westmereep-dp,core

GenuineIntel-6-25,v2,westmereep-sp,core

GenuineIntel-6-2F,v2,westmereex,core

GenuineIntel-6-55,v1,skylakex,core

tools/perf/pmu-events/arch/x86/skylakex/cache.json

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tools/perf/pmu-events/arch/x86/skylakex/floating-point.json

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[

    {

        "EventCode": "0xC7",

        "UMask": "0x1",

        "BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired.  Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",

        "Counter": "0,1,2,3",

        "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "EventCode": "0xC7",

        "UMask": "0x2",

        "BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired.  Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",

        "Counter": "0,1,2,3",

        "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "EventCode": "0xC7",

        "UMask": "0x4",

        "BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired.  Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",

        "Counter": "0,1,2,3",

        "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "EventCode": "0xC7",

        "UMask": "0x8",

        "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired.  Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.  ",

        "Counter": "0,1,2,3",

        "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",

        "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired.  Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "EventCode": "0xC7",

        "UMask": "0x10",

        "BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired.  Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",

        "Counter": "0,1,2,3",

        "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "EventCode": "0xC7",

        "UMask": "0x20",

        "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired.  Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",

        "Counter": "0,1,2,3",

        "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "EventCode": "0xC7",

        "UMask": "0x40",

        "BriefDescription": "Number of Packed Double-Precision FP arithmetic instructions (Use operation multiplier of 8)",

        "Counter": "0,1,2,3",

        "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE",

        "PublicDescription": "Number of Packed Double-Precision FP arithmetic instructions (Use operation multiplier of 8).",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "EventCode": "0xC7",

        "UMask": "0x80",

        "BriefDescription": "Number of Packed Single-Precision FP arithmetic instructions (Use operation multiplier of 16)",

        "Counter": "0,1,2,3",

        "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE",

        "PublicDescription": "Number of Packed Single-Precision FP arithmetic instructions (Use operation multiplier of 16).",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "EventCode": "0xCA",

        "UMask": "0x1e",

        "BriefDescription": "Cycles with any input/output SSE or FP assist",

        "Counter": "0,1,2,3",

        "EventName": "FP_ASSIST.ANY",

        "CounterMask": "1",

        "PublicDescription": "Counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1.",

        "SampleAfterValue": "100003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    }

]
 
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tools/perf/pmu-events/arch/x86/skylakex/frontend.json

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tools/perf/pmu-events/arch/x86/skylakex/memory.json

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