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Commit 62fd1a9f authored by Naveen Yadav's avatar Naveen Yadav
Browse files

clk: qcom: alpha: Update steps to slew the Lucid PLL 



When a set_rate request comes in for the Lucid PLL, the
poll for pll_ack_latch bit to be asserted can be bypassed
in SW programming. So adding flag SUPPORTS_NO_PLL_LATCH to
check the above condition.

Also update the bit for LUCID_PCAL_DONE to check process
calibration complete status from pll_mode register.

Change-Id: Ifc184e3620f0c24c670679d8a96ff5f599a7a4a9
Signed-off-by: default avatarNaveen Yadav <naveenky@codeaurora.org>
parent 5598d766

drivers/clk/qcom/clk-alpha-pll.c

+14 −9
Original line number Diff line number Diff line
@@ -158,7 +158,7 @@ 
#define LUCID_PLL_STANDBY		0x0

#define LUCID_PLL_RUN			0x1

#define LUCID_PLL_OUT_MASK		0x7

#define LUCID_PCAL_DONE			BIT(26)

#define LUCID_PCAL_DONE			BIT(27)

#define LUCID_PLL_RATE_MARGIN		500

#define LUCID_PLL_ACK_LATCH		BIT(29)

#define LUCID_PLL_UPDATE		BIT(22)
@@ -2553,8 +2553,7 @@ static int alpha_pll_lucid_prepare(struct clk_hw *hw) 
		return 0;



	/* Return early if calibration is not needed. */

	ret = regmap_read(pll->clkr.regmap, pll->offset + LUCID_PLL_OFF_STATUS,

		      &regval);

	ret = regmap_read(pll->clkr.regmap, pll->offset, &regval);

	if (regval & LUCID_PCAL_DONE)

		return ret;
@@ -2626,6 +2625,11 @@ static int alpha_pll_lucid_set_rate(struct clk_hw *hw, unsigned long rate, 
	if (ret)

		return ret;



	/*

	 * When PLL_HW_UPDATE_LOGIC_BYPASS bit is not set then waiting for

	 * pll_ack_latch to return to zero can be bypassed.

	 */

	if (!(pll->flags & SUPPORTS_NO_PLL_LATCH)) {

		/* Wait for 2 reference cycles before checking the ACK bit. */

		udelay(1);

		regmap_read(pll->clkr.regmap, pll->offset + PLL_MODE, &regval);
@@ -2633,6 +2637,7 @@ static int alpha_pll_lucid_set_rate(struct clk_hw *hw, unsigned long rate, 
			WARN(1, "PLL latch failed. Output may be unstable!\n");

			return -EINVAL;

		}

	}



	/* Return the latch input to 0 */

	ret = regmap_update_bits(pll->clkr.regmap, pll->offset + PLL_MODE,

drivers/clk/qcom/clk-alpha-pll.h

+2 −1
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2015, 2017-2018, The Linux Foundation. All rights reserved.

 * Copyright (c) 2015, 2017-2019, The Linux Foundation. All rights reserved.

 *

 * This software is licensed under the terms of the GNU General Public

 * License version 2, as published by the Free Software Foundation, and
@@ -77,6 +77,7 @@ struct clk_alpha_pll { 
	/* Associated with soft_vote for multiple PLL software instances */

#define SUPPORTS_FSM_VOTE	BIT(5)

#define SUPPORTS_NO_SLEW	BIT(6)

#define SUPPORTS_NO_PLL_LATCH	BIT(7)

	u8 flags;



	struct clk_regmap clkr;