Loading arch/arm64/boot/dts/qcom/sdmmagpie.dtsi +84 −0 Original line number Diff line number Diff line Loading @@ -51,6 +51,8 @@ compatible = "arm,armv8"; reg = <0x0 0x0>; enable-method = "psci"; capacity-dmips-mhz = <1024>; sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; cache-size = <0x8000>; next-level-cache = <&L2_0>; L2_0: l2-cache { Loading Loading @@ -86,6 +88,8 @@ compatible = "arm,armv8"; reg = <0x0 0x100>; enable-method = "psci"; capacity-dmips-mhz = <1024>; sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; cache-size = <0x8000>; next-level-cache = <&L2_100>; L2_100: l2-cache { Loading Loading @@ -116,6 +120,8 @@ compatible = "arm,armv8"; reg = <0x0 0x200>; enable-method = "psci"; capacity-dmips-mhz = <1024>; sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; cache-size = <0x8000>; next-level-cache = <&L2_200>; L2_200: l2-cache { Loading Loading @@ -145,6 +151,8 @@ compatible = "arm,armv8"; reg = <0x0 0x300>; enable-method = "psci"; capacity-dmips-mhz = <1024>; sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; cache-size = <0x8000>; next-level-cache = <&L2_300>; L2_300: l2-cache { Loading Loading @@ -174,6 +182,8 @@ compatible = "arm,armv8"; reg = <0x0 0x400>; enable-method = "psci"; capacity-dmips-mhz = <1024>; sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; cache-size = <0x8000>; next-level-cache = <&L2_400>; L2_400: l2-cache { Loading Loading @@ -203,6 +213,8 @@ compatible = "arm,armv8"; reg = <0x0 0x500>; enable-method = "psci"; capacity-dmips-mhz = <1024>; sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; cache-size = <0x8000>; next-level-cache = <&L2_500>; L2_500: l2-cache { Loading Loading @@ -232,6 +244,8 @@ compatible = "arm,armv8"; reg = <0x0 0x600>; enable-method = "psci"; capacity-dmips-mhz = <1740>; sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>; cache-size = <0x10000>; next-level-cache = <&L2_600>; L2_600: l2-cache { Loading Loading @@ -270,6 +284,8 @@ compatible = "arm,armv8"; reg = <0x0 0x700>; enable-method = "psci"; capacity-dmips-mhz = <1740>; sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>; cache-size = <0x10000>; next-level-cache = <&L2_700>; L2_700: l2-cache { Loading Loading @@ -343,6 +359,74 @@ }; }; energy_costs: energy-costs { compatible = "sched-energy"; CPU_COST_0: core-cost0 { busy-cost-data = < 300000 18 768000 23 1017600 36 1248000 52 1497600 76 1612800 92 1804800 119 >; idle-cost-data = < 16 12 8 6 >; }; CPU_COST_1: core-cost1 { busy-cost-data = < 300000 166 806400 293 1094400 470 1324800 676 1708800 1060 1939200 1362 2169600 1801 2361600 2326 2438400 2568 >; idle-cost-data = < 100 80 60 40 >; }; CLUSTER_COST_0: cluster-cost0 { busy-cost-data = < 300000 5 768000 5 1017600 7 1248000 8 1497600 10 1612800 12 1804800 14 >; idle-cost-data = < 4 3 2 1 >; }; CLUSTER_COST_1: cluster-cost1 { busy-cost-data = < 300000 19 806400 21 1094400 26 1324800 33 1708800 43 1939200 50 2169600 60 2361600 62 2438400 63 >; idle-cost-data = < 4 3 2 1 >; }; }; psci { compatible = "arm,psci-1.0"; method = "smc"; Loading Loading
arch/arm64/boot/dts/qcom/sdmmagpie.dtsi +84 −0 Original line number Diff line number Diff line Loading @@ -51,6 +51,8 @@ compatible = "arm,armv8"; reg = <0x0 0x0>; enable-method = "psci"; capacity-dmips-mhz = <1024>; sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; cache-size = <0x8000>; next-level-cache = <&L2_0>; L2_0: l2-cache { Loading Loading @@ -86,6 +88,8 @@ compatible = "arm,armv8"; reg = <0x0 0x100>; enable-method = "psci"; capacity-dmips-mhz = <1024>; sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; cache-size = <0x8000>; next-level-cache = <&L2_100>; L2_100: l2-cache { Loading Loading @@ -116,6 +120,8 @@ compatible = "arm,armv8"; reg = <0x0 0x200>; enable-method = "psci"; capacity-dmips-mhz = <1024>; sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; cache-size = <0x8000>; next-level-cache = <&L2_200>; L2_200: l2-cache { Loading Loading @@ -145,6 +151,8 @@ compatible = "arm,armv8"; reg = <0x0 0x300>; enable-method = "psci"; capacity-dmips-mhz = <1024>; sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; cache-size = <0x8000>; next-level-cache = <&L2_300>; L2_300: l2-cache { Loading Loading @@ -174,6 +182,8 @@ compatible = "arm,armv8"; reg = <0x0 0x400>; enable-method = "psci"; capacity-dmips-mhz = <1024>; sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; cache-size = <0x8000>; next-level-cache = <&L2_400>; L2_400: l2-cache { Loading Loading @@ -203,6 +213,8 @@ compatible = "arm,armv8"; reg = <0x0 0x500>; enable-method = "psci"; capacity-dmips-mhz = <1024>; sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; cache-size = <0x8000>; next-level-cache = <&L2_500>; L2_500: l2-cache { Loading Loading @@ -232,6 +244,8 @@ compatible = "arm,armv8"; reg = <0x0 0x600>; enable-method = "psci"; capacity-dmips-mhz = <1740>; sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>; cache-size = <0x10000>; next-level-cache = <&L2_600>; L2_600: l2-cache { Loading Loading @@ -270,6 +284,8 @@ compatible = "arm,armv8"; reg = <0x0 0x700>; enable-method = "psci"; capacity-dmips-mhz = <1740>; sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>; cache-size = <0x10000>; next-level-cache = <&L2_700>; L2_700: l2-cache { Loading Loading @@ -343,6 +359,74 @@ }; }; energy_costs: energy-costs { compatible = "sched-energy"; CPU_COST_0: core-cost0 { busy-cost-data = < 300000 18 768000 23 1017600 36 1248000 52 1497600 76 1612800 92 1804800 119 >; idle-cost-data = < 16 12 8 6 >; }; CPU_COST_1: core-cost1 { busy-cost-data = < 300000 166 806400 293 1094400 470 1324800 676 1708800 1060 1939200 1362 2169600 1801 2361600 2326 2438400 2568 >; idle-cost-data = < 100 80 60 40 >; }; CLUSTER_COST_0: cluster-cost0 { busy-cost-data = < 300000 5 768000 5 1017600 7 1248000 8 1497600 10 1612800 12 1804800 14 >; idle-cost-data = < 4 3 2 1 >; }; CLUSTER_COST_1: cluster-cost1 { busy-cost-data = < 300000 19 806400 21 1094400 26 1324800 33 1708800 43 1939200 50 2169600 60 2361600 62 2438400 63 >; idle-cost-data = < 4 3 2 1 >; }; }; psci { compatible = "arm,psci-1.0"; method = "smc"; Loading