Loading arch/arm/mach-omap2/cm4xxx.c +2 −15 Original line number Diff line number Diff line Loading @@ -22,7 +22,6 @@ #include <asm/atomic.h> #include "cm.h" #include "cm-regbits-4xxx.h" /* XXX move this to cm.h */ /* MAX_MODULE_READY_TIME: max milliseconds for module to leave idle */ Loading Loading @@ -50,19 +49,7 @@ */ int omap4_cm_wait_idlest_ready(u32 prcm_mod, u8 prcm_dev_offs) { int i = 0; u8 cm_id; u16 prcm_mod_offs; u32 mask = OMAP4_PRCM_CM_CLKCTRL_IDLEST_MASK; cm_id = prcm_mod >> OMAP4_PRCM_MOD_CM_ID_SHIFT; prcm_mod_offs = prcm_mod & OMAP4_PRCM_MOD_OFFS_MASK; while (((omap4_cm_read_mod_reg(cm_id, prcm_mod_offs, prcm_dev_offs, OMAP4_CM_CLKCTRL_DREG) & mask) != 0) && (i++ < MAX_MODULE_READY_TIME)) udelay(1); return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; /* FIXME: Add clock manager related code */ return 0; } arch/arm/mach-omap2/io.c +2 −2 Original line number Diff line number Diff line Loading @@ -294,10 +294,10 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0, else if (cpu_is_omap34xx()) hwmods = omap34xx_hwmods; omap_hwmod_init(hwmods); omap2_mux_init(); #ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once the clkdev is ready */ /* The OPP tables have to be registered before a clk init */ omap_hwmod_init(hwmods); omap2_mux_init(); omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps); pwrdm_init(powerdomains_omap); clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps); Loading arch/arm/mach-omap2/serial.c +1 −1 Original line number Diff line number Diff line Loading @@ -579,7 +579,7 @@ static struct omap_uart_state omap_uart[OMAP_MAX_NR_PORTS] = { { .pdev = { .name = "serial8250", .id = 3 .id = 3, .dev = { .platform_data = serial_platform_data3, }, Loading Loading
arch/arm/mach-omap2/cm4xxx.c +2 −15 Original line number Diff line number Diff line Loading @@ -22,7 +22,6 @@ #include <asm/atomic.h> #include "cm.h" #include "cm-regbits-4xxx.h" /* XXX move this to cm.h */ /* MAX_MODULE_READY_TIME: max milliseconds for module to leave idle */ Loading Loading @@ -50,19 +49,7 @@ */ int omap4_cm_wait_idlest_ready(u32 prcm_mod, u8 prcm_dev_offs) { int i = 0; u8 cm_id; u16 prcm_mod_offs; u32 mask = OMAP4_PRCM_CM_CLKCTRL_IDLEST_MASK; cm_id = prcm_mod >> OMAP4_PRCM_MOD_CM_ID_SHIFT; prcm_mod_offs = prcm_mod & OMAP4_PRCM_MOD_OFFS_MASK; while (((omap4_cm_read_mod_reg(cm_id, prcm_mod_offs, prcm_dev_offs, OMAP4_CM_CLKCTRL_DREG) & mask) != 0) && (i++ < MAX_MODULE_READY_TIME)) udelay(1); return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; /* FIXME: Add clock manager related code */ return 0; }
arch/arm/mach-omap2/io.c +2 −2 Original line number Diff line number Diff line Loading @@ -294,10 +294,10 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0, else if (cpu_is_omap34xx()) hwmods = omap34xx_hwmods; omap_hwmod_init(hwmods); omap2_mux_init(); #ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once the clkdev is ready */ /* The OPP tables have to be registered before a clk init */ omap_hwmod_init(hwmods); omap2_mux_init(); omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps); pwrdm_init(powerdomains_omap); clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps); Loading
arch/arm/mach-omap2/serial.c +1 −1 Original line number Diff line number Diff line Loading @@ -579,7 +579,7 @@ static struct omap_uart_state omap_uart[OMAP_MAX_NR_PORTS] = { { .pdev = { .name = "serial8250", .id = 3 .id = 3, .dev = { .platform_data = serial_platform_data3, }, Loading