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Commit 61b2bbd1 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
Browse files

Merge "ARM: dts: msm: Update USB QMP PHY configuration on sdxprairie"

parents 6c457fab a520a734

arch/arm64/boot/dts/qcom/sdxprairie-usb.dtsi

+13 −13
Original line number Diff line number Diff line
@@ -193,6 +193,7 @@ 
		     USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE1 0x36 0

		     USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xca 0

		     USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1e 0

		     USB3_UNI_QSERDES_COM_CMN_IPTRIM 0x20 0

		     USB3_UNI_QSERDES_COM_SSC_EN_CENTER 0x01 0

		     USB3_UNI_QSERDES_COM_SSC_PER1 0x31 0

		     USB3_UNI_QSERDES_COM_SSC_PER2 0x01 0
@@ -201,14 +202,13 @@ 
		     USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xde 0

		     USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07 0

		     USB3_UNI_QSERDES_COM_VCO_TUNE_MAP 0x02 0

		     USB3_UNI_QSERDES_COM_CMN_IPTRIM 0x20 0

		     USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH4 0x8c 0

		     USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH3 0x7f 0

		     USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2 0xff 0

		     USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH 0x3f 0

		     USB3_UNI_QSERDES_RX_RX_MODE_00_LOW 0xff 0

		     USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4 0xbc 0

		     USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH3 0x0b 0

		     USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4 0xb4 0

		     USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH3 0x7b 0

		     USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH2 0x5c 0

		     USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH 0xdc 0

		     USB3_UNI_QSERDES_RX_RX_MODE_01_LOW 0xdc 0
@@ -221,9 +221,9 @@ 
		     USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW 0xff 0

		     USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH 0x0f 0

		     USB3_UNI_QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x7f 0

		     USB3_UNI_QSERDES_RX_UCDR_FO_GAIN 0x0a 0

		     USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL1 0x54 0

		     USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL2 0x0c 0

		     USB3_UNI_QSERDES_RX_GM_CAL 0x1f 0

		     USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0f 0

		     USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x4a 0

		     USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0a 0
@@ -236,28 +236,28 @@ 
		     USB3_UNI_QSERDES_RX_RX_IDAC_TSETTLE_LOW 0xc0 0

		     USB3_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET 0x00 0

		     USB3_UNI_QSERDES_RX_UCDR_SO_GAIN 0x06 0

		     USB3_UNI_QSERDES_RX_DCC_CTRL1 0x0c 0

		     USB3_UNI_QSERDES_RX_GM_CAL 0x1f 0

		     USB3_UNI_QSERDES_TX_RCV_DETECT_LVL_2 0x12 0

		     USB3_UNI_QSERDES_TX_LANE_MODE_1 0xd5 0

		     USB3_UNI_QSERDES_RX_DCC_CTRL1 0x0c 0

		     USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX 0x08 0

		     USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_RX 0x00 0

		     USB3_UNI_QSERDES_TX_PI_QEC_CTRL 0x20 0

		     USB3_UNI_QSERDES_RX_UCDR_FO_GAIN 0x0a 0

		     USB3_UNI_QSERDES_TX_RES_CODE_LANE_TX 0x60 0

		     USB3_UNI_QSERDES_TX_RES_CODE_LANE_RX 0x60 0

		     USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX 0x08 0

		     USB3_UNI_PCS_LOCK_DETECT_CONFIG1 0xd0 0

		     USB3_UNI_PCS_LOCK_DETECT_CONFIG2 0x17 0

		     USB3_UNI_PCS_LOCK_DETECT_CONFIG2 0x07 0

		     USB3_UNI_PCS_LOCK_DETECT_CONFIG3 0x20 0

		     USB3_UNI_PCS_LOCK_DETECT_CONFIG6 0x13 0

		     USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_L 0xe7 0

		     USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_H 0x03 0

		     USB3_UNI_PCS_RX_SIGDET_LVL 0xaa 0

		     USB3_UNI_PCS_PCS_TX_RX_CONFIG 0x0c 0

		     USB3_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07 0

		     USB3_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xf8 0

		     USB3_UNI_PCS_CDR_RESET_TIME 0x0a 0

		     USB3_UNI_PCS_ALIGN_DETECT_CONFIG1 0x88 0

		     USB3_UNI_PCS_ALIGN_DETECT_CONFIG2 0x13 0

		     USB3_UNI_PCS_EQ_CONFIG1 0x0d 0

		     USB3_UNI_PCS_EQ_CONFIG1 0x4b 0

		     USB3_UNI_PCS_EQ_CONFIG5 0x10 0

		     USB3_UNI_PCS_REFGEN_REQ_CONFIG1 0x21 0

		     USB3_UNI_PCS_CDR_RESET_TIME 0x02 0

		     0xffffffff 0xffffffff 0x00>;



		qcom,qmp-phy-reg-offset =