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Commit 61a6976b authored by Paul Mundt's avatar Paul Mundt
Browse files

serial: sh-sci: Abstract register maps. 



This takes a bit of a sledgehammer to the horribly CPU subtype
ifdef-ridden header and abstracts all of the different register layouts
in to distinct types which in turn can be overriden on a per-port basis,
or permitted to default to the map matching the port type at probe time.

In the process this ultimately fixes up inumerable bugs with mismatches
on various CPU types (particularly the legacy ones that were obviously
broken years ago and no one noticed) and provides a more tightly coupled
and consolidated platform for extending and implementing generic
features.

Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
parent e1319889

arch/sh/Makefile

+1 −0
Original line number Original line Diff line number Diff line
@@ -173,6 +173,7 @@ core-$(CONFIG_HD6446X_SERIES) += arch/sh/cchips/hd6446x/ 
cpuincdir-$(CONFIG_CPU_SH2A)	+= cpu-sh2a

cpuincdir-$(CONFIG_CPU_SH2A)	+= cpu-sh2a

cpuincdir-$(CONFIG_CPU_SH2)	+= cpu-sh2

cpuincdir-$(CONFIG_CPU_SH2)	+= cpu-sh2

cpuincdir-$(CONFIG_CPU_SH3)	+= cpu-sh3

cpuincdir-$(CONFIG_CPU_SH3)	+= cpu-sh3

cpuincdir-$(CONFIG_CPU_SH4A)	+= cpu-sh4a

cpuincdir-$(CONFIG_CPU_SH4)	+= cpu-sh4

cpuincdir-$(CONFIG_CPU_SH4)	+= cpu-sh4

cpuincdir-$(CONFIG_CPU_SH5)	+= cpu-sh5

cpuincdir-$(CONFIG_CPU_SH5)	+= cpu-sh5

cpuincdir-y			+= cpu-common	# Must be last

cpuincdir-y			+= cpu-common	# Must be last

arch/sh/include/cpu-sh3/cpu/serial.h

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+10 −0
Original line number Original line Diff line number Diff line 
#ifndef __CPU_SH3_SERIAL_H

#define __CPU_SH3_SERIAL_H



#include <linux/serial_sci.h>



extern struct plat_sci_port_ops sh770x_sci_port_ops;

extern struct plat_sci_port_ops sh7710_sci_port_ops;

extern struct plat_sci_port_ops sh7720_sci_port_ops;



#endif /* __CPU_SH3_SERIAL_H */

arch/sh/include/cpu-sh4a/cpu/serial.h

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+7 −0
Original line number Original line Diff line number Diff line 
#ifndef __CPU_SH4A_SERIAL_H

#define __CPU_SH4A_SERIAL_H



/* arch/sh/kernel/cpu/sh4a/serial-sh7722.c */

extern struct plat_sci_port_ops sh7722_sci_port_ops;



#endif /* __CPU_SH4A_SERIAL_H */

arch/sh/kernel/cpu/sh3/Makefile

+9 −9
Original line number Original line Diff line number Diff line
@@ -7,15 +7,15 @@ obj-y := ex.o probe.o entry.o setup-sh3.o 
obj-$(CONFIG_HIBERNATION)		+= swsusp.o

obj-$(CONFIG_HIBERNATION)		+= swsusp.o





# CPU subtype setup

# CPU subtype setup

obj-$(CONFIG_CPU_SUBTYPE_SH7705)	+= setup-sh7705.o

obj-$(CONFIG_CPU_SUBTYPE_SH7705)	+= setup-sh7705.o serial-sh770x.o

obj-$(CONFIG_CPU_SUBTYPE_SH7706)	+= setup-sh770x.o

obj-$(CONFIG_CPU_SUBTYPE_SH7706)	+= setup-sh770x.o serial-sh770x.o

obj-$(CONFIG_CPU_SUBTYPE_SH7707)	+= setup-sh770x.o

obj-$(CONFIG_CPU_SUBTYPE_SH7707)	+= setup-sh770x.o serial-sh770x.o

obj-$(CONFIG_CPU_SUBTYPE_SH7708)	+= setup-sh770x.o

obj-$(CONFIG_CPU_SUBTYPE_SH7708)	+= setup-sh770x.o serial-sh770x.o

obj-$(CONFIG_CPU_SUBTYPE_SH7709)	+= setup-sh770x.o

obj-$(CONFIG_CPU_SUBTYPE_SH7709)	+= setup-sh770x.o serial-sh770x.o

obj-$(CONFIG_CPU_SUBTYPE_SH7710)	+= setup-sh7710.o

obj-$(CONFIG_CPU_SUBTYPE_SH7710)	+= setup-sh7710.o serial-sh7710.o

obj-$(CONFIG_CPU_SUBTYPE_SH7712)	+= setup-sh7710.o

obj-$(CONFIG_CPU_SUBTYPE_SH7712)	+= setup-sh7710.o serial-sh7710.o

obj-$(CONFIG_CPU_SUBTYPE_SH7720)	+= setup-sh7720.o

obj-$(CONFIG_CPU_SUBTYPE_SH7720)	+= setup-sh7720.o serial-sh7720.o

obj-$(CONFIG_CPU_SUBTYPE_SH7721)	+= setup-sh7720.o

obj-$(CONFIG_CPU_SUBTYPE_SH7721)	+= setup-sh7720.o serial-sh7720.o





# Primary on-chip clocks (common)

# Primary on-chip clocks (common)

clock-$(CONFIG_CPU_SH3)			:= clock-sh3.o

clock-$(CONFIG_CPU_SH3)			:= clock-sh3.o

arch/sh/kernel/cpu/sh3/serial-sh770x.c

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+33 −0
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#include <linux/serial_sci.h>

#include <linux/serial_core.h>

#include <linux/io.h>

#include <cpu/serial.h>



#define SCPCR 0xA4000116

#define SCPDR 0xA4000136



static void sh770x_sci_init_pins(struct uart_port *port, unsigned int cflag)

{

	unsigned short data;



	/* We need to set SCPCR to enable RTS/CTS */

	data = __raw_readw(SCPCR);

	/* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/

	__raw_writew(data & 0x0fcf, SCPCR);



	if (!(cflag & CRTSCTS)) {

		/* We need to set SCPCR to enable RTS/CTS */

		data = __raw_readw(SCPCR);

		/* Clear out SCP7MD1,0, SCP4MD1,0,

		   Set SCP6MD1,0 = {01} (output)  */

		__raw_writew((data & 0x0fcf) | 0x1000, SCPCR);



		data = __raw_readb(SCPDR);

		/* Set /RTS2 (bit6) = 0 */

		__raw_writeb(data & 0xbf, SCPDR);

	}

}



struct plat_sci_port_ops sh770x_sci_port_ops = {

	.init_pins	= sh770x_sci_init_pins,

};