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Commit 6198dd8d authored by Hariprasad S's avatar Hariprasad S Committed by Doug Ledford
Browse files

iw_cxgb4: 32b platform fixes 



- get_dma_mr() was using ~0UL which is should be ~0ULL.  This causes the
DMA MR to get setup incorrectly in hardware.

- wr_log_show() needed a 64b divide function div64_u64() instead of
  doing
division directly.

- fixed warnings about recasting a pointer to a u64

Signed-off-by: default avatarSteve Wise <swise@opengridcomputing.com>
Signed-off-by: default avatarHariprasad Shenai <hariprasad@chelsio.com>
Signed-off-by: default avatarDoug Ledford <dledford@redhat.com>
parent 0b741047

drivers/infiniband/hw/cxgb4/cm.c

+1 −1
Original line number Diff line number Diff line
@@ -3571,7 +3571,7 @@ static void send_fw_pass_open_req(struct c4iw_dev *dev, struct sk_buff *skb, 
	 * TP will ignore any value > 0 for MSS index.

	 */

	req->tcb.opt0 = cpu_to_be64(MSS_IDX_V(0xF));

	req->cookie = (unsigned long)skb;

	req->cookie = (uintptr_t)skb;



	set_wr_txq(req_skb, CPL_PRIORITY_CONTROL, port_id);

	ret = cxgb4_ofld_send(dev->rdev.lldi.ports[0], req_skb);

drivers/infiniband/hw/cxgb4/cq.c

+3 −4
Original line number Diff line number Diff line
@@ -55,7 +55,7 @@ static int destroy_cq(struct c4iw_rdev *rdev, struct t4_cq *cq, 
			FW_RI_RES_WR_NRES_V(1) |

			FW_WR_COMPL_F);

	res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));

	res_wr->cookie = (unsigned long) &wr_wait;

	res_wr->cookie = (uintptr_t)&wr_wait;

	res = res_wr->res;

	res->u.cq.restype = FW_RI_RES_TYPE_CQ;

	res->u.cq.op = FW_RI_RES_OP_RESET;
@@ -125,7 +125,7 @@ static int create_cq(struct c4iw_rdev *rdev, struct t4_cq *cq, 
			FW_RI_RES_WR_NRES_V(1) |

			FW_WR_COMPL_F);

	res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));

	res_wr->cookie = (unsigned long) &wr_wait;

	res_wr->cookie = (uintptr_t)&wr_wait;

	res = res_wr->res;

	res->u.cq.restype = FW_RI_RES_TYPE_CQ;

	res->u.cq.op = FW_RI_RES_OP_WRITE;
@@ -970,8 +970,7 @@ struct ib_cq *c4iw_create_cq(struct ib_device *ibdev, int entries, 
	}

	PDBG("%s cqid 0x%0x chp %p size %u memsize %zu, dma_addr 0x%0llx\n",

	     __func__, chp->cq.cqid, chp, chp->cq.size,

	     chp->cq.memsize,

	     (unsigned long long) chp->cq.dma_addr);

	     chp->cq.memsize, (unsigned long long) chp->cq.dma_addr);

	return &chp->ibcq;

err5:

	kfree(mm2);

drivers/infiniband/hw/cxgb4/device.c

+3 −3
Original line number Diff line number Diff line
@@ -151,7 +151,7 @@ static int wr_log_show(struct seq_file *seq, void *v) 
	int prev_ts_set = 0;

	int idx, end;



#define ts2ns(ts) div64_ul((ts) * dev->rdev.lldi.cclk_ps, 1000)

#define ts2ns(ts) div64_u64((ts) * dev->rdev.lldi.cclk_ps, 1000)



	idx = atomic_read(&dev->rdev.wr_log_idx) &

		(dev->rdev.wr_log_size - 1);
@@ -784,10 +784,10 @@ static int c4iw_rdev_open(struct c4iw_rdev *rdev) 
	     rdev->lldi.vr->qp.size,

	     rdev->lldi.vr->cq.start,

	     rdev->lldi.vr->cq.size);

	PDBG("udb len 0x%x udb base %llx db_reg %p gts_reg %p qpshift %lu "

	PDBG("udb len 0x%x udb base %p db_reg %p gts_reg %p qpshift %lu "

	     "qpmask 0x%x cqshift %lu cqmask 0x%x\n",

	     (unsigned)pci_resource_len(rdev->lldi.pdev, 2),

	     (u64)pci_resource_start(rdev->lldi.pdev, 2),

	     (void *)pci_resource_start(rdev->lldi.pdev, 2),

	     rdev->lldi.db_reg,

	     rdev->lldi.gts_reg,

	     rdev->qpshift, rdev->qpmask,

drivers/infiniband/hw/cxgb4/mem.c

+3 −3
Original line number Diff line number Diff line
@@ -144,7 +144,7 @@ static int _c4iw_write_mem_inline(struct c4iw_rdev *rdev, u32 addr, u32 len, 
		if (i == (num_wqe-1)) {

			req->wr.wr_hi = cpu_to_be32(FW_WR_OP_V(FW_ULPTX_WR) |

						    FW_WR_COMPL_F);

			req->wr.wr_lo = (__force __be64)(unsigned long) &wr_wait;

			req->wr.wr_lo = (__force __be64)&wr_wait;

		} else

			req->wr.wr_hi = cpu_to_be32(FW_WR_OP_V(FW_ULPTX_WR));

		req->wr.wr_mid = cpu_to_be32(
@@ -676,12 +676,12 @@ struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc) 
	mhp->attr.zbva = 0;

	mhp->attr.va_fbo = 0;

	mhp->attr.page_size = 0;

	mhp->attr.len = ~0UL;

	mhp->attr.len = ~0ULL;

	mhp->attr.pbl_size = 0;



	ret = write_tpt_entry(&rhp->rdev, 0, &stag, 1, php->pdid,

			      FW_RI_STAG_NSMR, mhp->attr.perms,

			      mhp->attr.mw_bind_enable, 0, 0, ~0UL, 0, 0, 0);

			      mhp->attr.mw_bind_enable, 0, 0, ~0ULL, 0, 0, 0);

	if (ret)

		goto err1;

drivers/infiniband/hw/cxgb4/qp.c

+5 −5
Original line number Diff line number Diff line
@@ -275,7 +275,7 @@ static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq, 
			FW_RI_RES_WR_NRES_V(2) |

			FW_WR_COMPL_F);

	res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));

	res_wr->cookie = (unsigned long) &wr_wait;

	res_wr->cookie = (uintptr_t)&wr_wait;

	res = res_wr->res;

	res->u.sqrq.restype = FW_RI_RES_TYPE_SQ;

	res->u.sqrq.op = FW_RI_RES_OP_WRITE;
@@ -1209,7 +1209,7 @@ static int rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp, 
	wqe->flowid_len16 = cpu_to_be32(

		FW_WR_FLOWID_V(ep->hwtid) |

		FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe), 16)));

	wqe->cookie = (unsigned long) &ep->com.wr_wait;

	wqe->cookie = (uintptr_t)&ep->com.wr_wait;



	wqe->u.fini.type = FW_RI_TYPE_FINI;

	ret = c4iw_ofld_send(&rhp->rdev, skb);
@@ -1279,7 +1279,7 @@ static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp) 
		FW_WR_FLOWID_V(qhp->ep->hwtid) |

		FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe), 16)));



	wqe->cookie = (unsigned long) &qhp->ep->com.wr_wait;

	wqe->cookie = (uintptr_t)&qhp->ep->com.wr_wait;



	wqe->u.init.type = FW_RI_TYPE_INIT;

	wqe->u.init.mpareqbit_p2ptype =