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Commit 6109e2ce authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6 

* 'linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6: (36 commits)
  PCI: hotplug: pciehp: Removed check for hotplug of display devices
  PCI: read memory ranges out of Broadcom CNB20LE host bridge
  PCI: Allow manual resource allocation for PCI hotplug bridges
  x86/PCI: make ACPI MCFG reserved error messages ACPI specific
  PCI hotplug: Use kmemdup
  PM/PCI: Update PCI power management documentation
  PCI: output FW warning in pci_read/write_vpd
  PCI: fix typos pci_device_dis/enable to pci_dis/enable_device in comments
  PCI quirks: disable msi on AMD rs4xx internal gfx bridges
  PCI: Disable MSI for MCP55 on P5N32-E SLI
  x86/PCI: irq and pci_ids patch for additional Intel Cougar Point DeviceIDs
  PCI: aerdrv: trivial cleanup for aerdrv_core.c
  PCI: aerdrv: trivial cleanup for aerdrv.c
  PCI: aerdrv: introduce default_downstream_reset_link
  PCI: aerdrv: rework find_aer_service
  PCI: aerdrv: remove is_downstream
  PCI: aerdrv: remove magical ROOT_ERR_STATUS_MASKS
  PCI: aerdrv: redefine PCI_ERR_ROOT_*_SRC
  PCI: aerdrv: rework do_recovery
  PCI: aerdrv: rework get_e_source()
  ...
parents 0961d658 ac81860e

Documentation/ABI/testing/sysfs-bus-pci

+40 −0
Original line number Diff line number Diff line
@@ -133,6 +133,46 @@ Description: 
		The symbolic link points to the PCI device sysfs entry of the

		Physical Function this device associates with.





What:		/sys/bus/pci/slots/...

Date:		April 2005 (possibly older)

KernelVersion:	2.6.12 (possibly older)

Contact:	linux-pci@vger.kernel.org

Description:

		When the appropriate driver is loaded, it will create a

		directory per claimed physical PCI slot in

		/sys/bus/pci/slots/.  The names of these directories are

		specific to the driver, which in turn, are specific to the

		platform, but in general, should match the label on the

		machine's physical chassis.



		The drivers that can create slot directories include the

		PCI hotplug drivers, and as of 2.6.27, the pci_slot driver.



		The slot directories contain, at a minimum, a file named

		'address' which contains the PCI bus:device:function tuple.

		Other files may appear as well, but are specific to the

		driver.



What:		/sys/bus/pci/slots/.../function[0-7]

Date:		March 2010

KernelVersion:	2.6.35

Contact:	linux-pci@vger.kernel.org

Description:

		If PCI slot directories (as described above) are created,

		and the physical slot is actually populated with a device,

		symbolic links in the slot directory pointing to the

		device's PCI functions are created as well.



What:		/sys/bus/pci/devices/.../slot

Date:		March 2010

KernelVersion:	2.6.35

Contact:	linux-pci@vger.kernel.org

Description:

		If PCI slot directories (as described above) are created,

		a symbolic link pointing to the slot directory will be

		created as well.



What:		/sys/bus/pci/slots/.../module

Date:		June 2009

Contact:	linux-pci@vger.kernel.org

Documentation/PCI/pcieaer-howto.txt

+13 −16
Original line number Diff line number Diff line
@@ -13,7 +13,7 @@ Reporting (AER) driver and provides information on how to use it, as 
well as how to enable the drivers of endpoint devices to conform with

PCI Express AER driver.



1.2 Copyright © Intel Corporation 2006.

1.2 Copyright (C) Intel Corporation 2006.



1.3 What is the PCI Express AER Driver?
@@ -71,15 +71,11 @@ console. If it's a correctable error, it is outputed as a warning. 
Otherwise, it is printed as an error. So users could choose different

log level to filter out correctable error messages.



Below shows an example.

+------ PCI-Express Device Error -----+

Error Severity          : Uncorrected (Fatal)

PCIE Bus Error type     : Transaction Layer

Unsupported Request     : First

Requester ID            : 0500

VendorID=8086h, DeviceID=0329h, Bus=05h, Device=00h, Function=00h

TLB Header:

04000001 00200a03 05010000 00050100

Below shows an example:

0000:50:00.0: PCIe Bus Error: severity=Uncorrected (Fatal), type=Transaction Layer, id=0500(Requester ID)

0000:50:00.0:   device [8086:0329] error status/mask=00100000/00000000

0000:50:00.0:    [20] Unsupported Request    (First)

0000:50:00.0:   TLP Header: 04000001 00200a03 05010000 00050100



In the example, 'Requester ID' means the ID of the device who sends

the error message to root port. Pls. refer to pci express specs for
@@ -112,7 +108,7 @@ but the PCI Express link itself is fully functional. Fatal errors, on 
the other hand, cause the link to be unreliable.



When AER is enabled, a PCI Express device will automatically send an

error message to the PCIE root port above it when the device captures

error message to the PCIe root port above it when the device captures

an error. The Root Port, upon receiving an error reporting message,

internally processes and logs the error message in its PCI Express

capability structure. Error information being logged includes storing
@@ -198,8 +194,9 @@ to reset link, AER port service driver is required to provide the 
function to reset link. Firstly, kernel looks for if the upstream

component has an aer driver. If it has, kernel uses the reset_link

callback of the aer driver. If the upstream component has no aer driver

and the port is downstream port, we will use the aer driver of the

root port who reports the AER error. As for upstream ports,

and the port is downstream port, we will perform a hot reset as the

default by setting the Secondary Bus Reset bit of the Bridge Control

register associated with the downstream port. As for upstream ports,

they should provide their own aer service drivers with reset_link

function. If error_detected returns PCI_ERS_RESULT_CAN_RECOVER and

reset_link returns PCI_ERS_RESULT_RECOVERED, the error handling goes
@@ -253,11 +250,11 @@ cleanup uncorrectable status register. Pls. refer to section 3.3. 


4. Software error injection



Debugging PCIE AER error recovery code is quite difficult because it

Debugging PCIe AER error recovery code is quite difficult because it

is hard to trigger real hardware errors. Software based error

injection can be used to fake various kinds of PCIE errors.

injection can be used to fake various kinds of PCIe errors.



First you should enable PCIE AER software error injection in kernel

First you should enable PCIe AER software error injection in kernel

configuration, that is, following item should be in your .config.



CONFIG_PCIEAER_INJECT=y or CONFIG_PCIEAER_INJECT=m

Documentation/power/pci.txt

+992 −266

File changed.

Preview size limit exceeded, changes collapsed.

arch/x86/Kconfig

+8 −0
Original line number Diff line number Diff line
@@ -1923,6 +1923,14 @@ config PCI_MMCONFIG 
	bool "Support mmconfig PCI config space access"

	depends on X86_64 && PCI && ACPI



config PCI_CNB20LE_QUIRK

	bool "Read CNB20LE Host Bridge Windows"

	depends on PCI

	help

	  Read the PCI windows out of the CNB20LE host bridge. This allows

	  PCI hotplug to work on systems with the CNB20LE chipset which do

	  not have ACPI.



config DMAR

	bool "Support for DMA Remapping Devices (EXPERIMENTAL)"

	depends on PCI_MSI && ACPI && EXPERIMENTAL

arch/x86/include/asm/pci_x86.h

+1 −1
Original line number Diff line number Diff line
@@ -83,7 +83,7 @@ struct irq_routing_table { 


extern unsigned int pcibios_irq_mask;



extern spinlock_t pci_config_lock;

extern raw_spinlock_t pci_config_lock;



extern int (*pcibios_enable_irq)(struct pci_dev *dev);

extern void (*pcibios_disable_irq)(struct pci_dev *dev);