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Commit 60d2d8dd authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'dp83867-impedance-control' 

Mugunthan V N says:

====================
add support for impedance control for TI dp83867 phy and fix 2nd ethernet on dra72 rev C evm

Add support for configurable impedance control for TI dp83867
phy via devicetree. More documentation in [1].
CPSW second ethernet is not working, fix it by enabling
impedance configuration on the phy.

Verified the patch on DRA72 Rev C evm, logs at [2]. Also pushed
a branch [3] for others to test.

Changes from v3:
* Fixup change log text and no code changes.

Changes from v2:
* Fixed a typo in dts and driver.

Changes from initial version:
* As per Sekhar's comment, instead of passing impedance values,
  change to max and min impedance from DT
* Adopted phy_read_mmd_indirect() to cunnrent implementation.
* Corrected the phy delay timings to the optimal value.

[1] - http://www.ti.com/lit/ds/symlink/dp83867ir.pdf
[2] - http://pastebin.ubuntu.com/23343139/
[3] - git://git.ti.com/~mugunthanvnm/ti-linux-kernel/linux.git

 dp83867-v4
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 403f0727 1f065544

Documentation/devicetree/bindings/net/ti,dp83867.txt

+12 −0
Original line number Diff line number Diff line
@@ -9,6 +9,18 @@ Required properties: 
	- ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h

		for applicable values



Optional property:

	- ti,min-output-impedance - MAC Interface Impedance control to set

				    the programmable output impedance to

				    minimum value (35 ohms).

	- ti,max-output-impedance - MAC Interface Impedance control to set

				    the programmable output impedance to

				    maximum value (70 ohms).



Note: ti,min-output-impedance and ti,max-output-impedance are mutually

      exclusive. When both properties are present ti,max-output-impedance

      takes precedence.



Default child nodes are standard Ethernet PHY device

nodes as described in Documentation/devicetree/bindings/net/phy.txt

arch/arm/boot/dts/dra72-evm-revc.dts

+6 −4
Original line number Diff line number Diff line
@@ -59,15 +59,17 @@ 
&davinci_mdio {

	dp83867_0: ethernet-phy@2 {

		reg = <2>;

		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;

		ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_NS>;

		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;

		ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;

		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;

		ti,min-output-impedance;

	};



	dp83867_1: ethernet-phy@3 {

		reg = <3>;

		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;

		ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_NS>;

		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;

		ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;

		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;

		ti,min-output-imepdance;

	};

};

drivers/net/phy/dp83867.c

+28 −0
Original line number Diff line number Diff line
@@ -33,6 +33,7 @@ 
/* Extended Registers */

#define DP83867_RGMIICTL	0x0032

#define DP83867_RGMIIDCTL	0x0086

#define DP83867_IO_MUX_CFG	0x0170



#define DP83867_SW_RESET	BIT(15)

#define DP83867_SW_RESTART	BIT(14)
@@ -62,10 +63,17 @@ 
/* RGMIIDCTL bits */

#define DP83867_RGMII_TX_CLK_DELAY_SHIFT	4



/* IO_MUX_CFG bits */

#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL	0x1f



#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX	0x0

#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN	0x1f



struct dp83867_private {

	int rx_id_delay;

	int tx_id_delay;

	int fifo_depth;

	int io_impedance;

};



static int dp83867_ack_interrupt(struct phy_device *phydev)
@@ -111,6 +119,14 @@ static int dp83867_of_init(struct phy_device *phydev) 
	if (!of_node)

		return -ENODEV;



	dp83867->io_impedance = -EINVAL;



	/* Optional configuration */

	if (of_property_read_bool(of_node, "ti,max-output-impedance"))

		dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;

	else if (of_property_read_bool(of_node, "ti,min-output-impedance"))

		dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;



	ret = of_property_read_u32(of_node, "ti,rx-internal-delay",

				   &dp83867->rx_id_delay);

	if (ret)
@@ -184,6 +200,18 @@ static int dp83867_config_init(struct phy_device *phydev) 


		phy_write_mmd_indirect(phydev, DP83867_RGMIIDCTL,

				       DP83867_DEVADDR, delay);



		if (dp83867->io_impedance >= 0) {

			val = phy_read_mmd_indirect(phydev, DP83867_IO_MUX_CFG,

						    DP83867_DEVADDR);



			val &= ~DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;

			val |= dp83867->io_impedance &

			       DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;



			phy_write_mmd_indirect(phydev, DP83867_IO_MUX_CFG,

					       DP83867_DEVADDR, val);

		}

	}



	return 0;