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Commit 5f086d3e authored by Ashok Vuyyuru's avatar Ashok Vuyyuru Committed by Gerrit - the friendly Code Review server
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msm: ipa4: Fix to change the header address to u64 



Because of using u32 header address in 64 bit targets losing
MSB 32-bit address. Updated the header address variable from u32 to u64

Change-Id: I26c88e4ebd86a441a02fc2fd93f8168eebf7aff4
Signed-off-by: default avatarAshok Vuyyuru <avuyyuru@codeaurora.org>
parent dc7aa950

drivers/platform/msm/ipa/ipa_v3/ipa_hdr.c

+4 −4
Original line number Diff line number Diff line 
/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.

/* Copyright (c) 2012-2019, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -62,7 +62,7 @@ static int ipa3_generate_hdr_hw_tbl(struct ipa_mem_buffer *mem) 
}



static int ipa3_hdr_proc_ctx_to_hw_format(struct ipa_mem_buffer *mem,

	u32 hdr_base_addr)

	u64 hdr_base_addr)

{

	struct ipa3_hdr_proc_ctx_entry *entry;

	int ret;
@@ -117,10 +117,10 @@ static int ipa3_hdr_proc_ctx_to_hw_format(struct ipa_mem_buffer *mem, 
 *

 * Returns:	0 on success, negative on failure

 */

static int ipa3_generate_hdr_proc_ctx_hw_tbl(u32 hdr_sys_addr,

static int ipa3_generate_hdr_proc_ctx_hw_tbl(u64 hdr_sys_addr,

	struct ipa_mem_buffer *mem, struct ipa_mem_buffer *aligned_mem)

{

	u32 hdr_base_addr;

	u64 hdr_base_addr;



	mem->size = (ipa3_ctx->hdr_proc_ctx_tbl.end) ? : 4;

drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal.c

+10 −10
Original line number Diff line number Diff line 
/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.

/* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -1204,7 +1204,7 @@ static void ipahal_cp_hdr_to_hw_buff_v3(void *const base, u32 offset, 
static int ipahal_cp_proc_ctx_to_hw_buff_v3(enum ipa_hdr_proc_type type,

		void *const base, u32 offset,

		u32 hdr_len, bool is_hdr_proc_ctx,

		dma_addr_t phys_base, u32 hdr_base_addr,

		dma_addr_t phys_base, u64 hdr_base_addr,

		struct ipa_hdr_offset_entry *offset_entry,

		struct ipa_l2tp_hdr_proc_ctx_params l2tp_params)

{
@@ -1218,7 +1218,7 @@ static int ipahal_cp_proc_ctx_to_hw_buff_v3(enum ipa_hdr_proc_type type, 
		ctx->hdr_add.tlv.value = hdr_len;

		ctx->hdr_add.hdr_addr = is_hdr_proc_ctx ? phys_base :

			hdr_base_addr + offset_entry->offset;

		IPAHAL_DBG("header address 0x%x\n",

		IPAHAL_DBG("header address 0x%llx\n",

			ctx->hdr_add.hdr_addr);

		ctx->end.type = IPA_PROC_CTX_TLV_TYPE_END;

		ctx->end.length = 0;
@@ -1233,7 +1233,7 @@ static int ipahal_cp_proc_ctx_to_hw_buff_v3(enum ipa_hdr_proc_type type, 
		ctx->hdr_add.tlv.value = hdr_len;

		ctx->hdr_add.hdr_addr = is_hdr_proc_ctx ? phys_base :

			hdr_base_addr + offset_entry->offset;

		IPAHAL_DBG("header address 0x%x\n",

		IPAHAL_DBG("header address 0x%llx\n",

			ctx->hdr_add.hdr_addr);

		ctx->l2tp_params.tlv.type = IPA_PROC_CTX_TLV_TYPE_PROC_CMD;

		ctx->l2tp_params.tlv.length = 1;
@@ -1260,7 +1260,7 @@ static int ipahal_cp_proc_ctx_to_hw_buff_v3(enum ipa_hdr_proc_type type, 
		ctx->hdr_add.tlv.value = hdr_len;

		ctx->hdr_add.hdr_addr = is_hdr_proc_ctx ? phys_base :

			hdr_base_addr + offset_entry->offset;

		IPAHAL_DBG("header address 0x%x length %d\n",

		IPAHAL_DBG("header address 0x%llx length %d\n",

			ctx->hdr_add.hdr_addr, ctx->hdr_add.tlv.value);

		ctx->l2tp_params.tlv.type = IPA_PROC_CTX_TLV_TYPE_PROC_CMD;

		ctx->l2tp_params.tlv.length = 1;
@@ -1296,7 +1296,7 @@ static int ipahal_cp_proc_ctx_to_hw_buff_v3(enum ipa_hdr_proc_type type, 
		ctx->hdr_add.tlv.value = hdr_len;

		ctx->hdr_add.hdr_addr = is_hdr_proc_ctx ? phys_base :

			hdr_base_addr + offset_entry->offset;

		IPAHAL_DBG("header address 0x%x\n",

		IPAHAL_DBG("header address 0x%llx\n",

			ctx->hdr_add.hdr_addr);

		ctx->cmd.type = IPA_PROC_CTX_TLV_TYPE_PROC_CMD;

		ctx->cmd.length = 0;
@@ -1353,7 +1353,7 @@ struct ipahal_hdr_funcs { 
	int (*ipahal_cp_proc_ctx_to_hw_buff)(enum ipa_hdr_proc_type type,

			void *const base, u32 offset, u32 hdr_len,

			bool is_hdr_proc_ctx, dma_addr_t phys_base,

			u32 hdr_base_addr,

			u64 hdr_base_addr,

			struct ipa_hdr_offset_entry *offset_entry,

			struct ipa_l2tp_hdr_proc_ctx_params l2tp_params);
@@ -1425,11 +1425,11 @@ void ipahal_cp_hdr_to_hw_buff(void *base, u32 offset, u8 *const hdr, 
int ipahal_cp_proc_ctx_to_hw_buff(enum ipa_hdr_proc_type type,

		void *const base, u32 offset, u32 hdr_len,

		bool is_hdr_proc_ctx, dma_addr_t phys_base,

		u32 hdr_base_addr, struct ipa_hdr_offset_entry *offset_entry,

		u64 hdr_base_addr, struct ipa_hdr_offset_entry *offset_entry,

		struct ipa_l2tp_hdr_proc_ctx_params l2tp_params)

{

	IPAHAL_DBG(

		"type %d, base %pK, offset %d, hdr_len %d, is_hdr_proc_ctx %d, hdr_base_addr %d, offset_entry %pK\n"

		"type %d, base %pK, offset %d, hdr_len %d, is_hdr_proc_ctx %d, hdr_base_addr %llu, offset_entry %pK\n"

			, type, base, offset, hdr_len, is_hdr_proc_ctx,

			hdr_base_addr, offset_entry);
@@ -1439,7 +1439,7 @@ int ipahal_cp_proc_ctx_to_hw_buff(enum ipa_hdr_proc_type type, 
		(!is_hdr_proc_ctx && !offset_entry) ||

		(!is_hdr_proc_ctx && !hdr_base_addr)) {

		IPAHAL_ERR(

			"invalid input: hdr_len:%u phys_base:%pad hdr_base_addr:%u is_hdr_proc_ctx:%d offset_entry:%pK\n"

			"invalid input: hdr_len:%u phys_base:%pad hdr_base_addr:%llu is_hdr_proc_ctx:%d offset_entry:%pK\n"

			, hdr_len, &phys_base, hdr_base_addr

			, is_hdr_proc_ctx, offset_entry);

		return -EINVAL;

drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal.h

+2 −2
Original line number Diff line number Diff line 
/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.

/* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -641,7 +641,7 @@ void ipahal_cp_hdr_to_hw_buff(void *base, u32 offset, u8 *hdr, u32 hdr_len); 
int ipahal_cp_proc_ctx_to_hw_buff(enum ipa_hdr_proc_type type,

		void *base, u32 offset, u32 hdr_len,

		bool is_hdr_proc_ctx, dma_addr_t phys_base,

		u32 hdr_base_addr,

		u64 hdr_base_addr,

		struct ipa_hdr_offset_entry *offset_entry,

		struct ipa_l2tp_hdr_proc_ctx_params l2tp_params);