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Commit 5ede49bb authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "drm/msm/sde: Update CSC matrix coefficient programming" into dev/msm-4.14-display

parents 38b9ea06 9befaff5

drivers/gpu/drm/msm/sde/sde_hw_sspp.c

+2 −1
Original line number Diff line number Diff line
@@ -150,6 +150,7 @@ 
#define VIG_CSC_10_SRC_DATAFMT BIT(1)

#define VIG_CSC_10_EN          BIT(0)

#define CSC_10BIT_OFFSET       4

#define DGM_CSC_MATRIX_SHIFT       0



/* traffic shaper clock in Hz */

#define TS_CLK			19200000
@@ -1053,7 +1054,7 @@ static void sde_hw_sspp_setup_dgm_csc(struct sde_hw_pipe *ctx, 
	if (data) {

		op_mode |= BIT(0);

		sde_hw_csc_matrix_coeff_setup(&ctx->hw,

			offset + CSC_10BIT_OFFSET, data);

			offset + CSC_10BIT_OFFSET, data, DGM_CSC_MATRIX_SHIFT);

	}



	SDE_REG_WRITE(&ctx->hw, offset, op_mode);

drivers/gpu/drm/msm/sde/sde_hw_util.c

+13 −12
Original line number Diff line number Diff line
@@ -373,27 +373,27 @@ u32 sde_hw_get_scaler3_ver(struct sde_hw_blk_reg_map *c, 
}



void sde_hw_csc_matrix_coeff_setup(struct sde_hw_blk_reg_map *c,

		u32 csc_reg_off, struct sde_csc_cfg *data)

		u32 csc_reg_off, struct sde_csc_cfg *data,

		u32 shift_bit)

{

	u32 val;



	if (!c || !data)

		return;



	/* matrix coeff - convert S15.16 to S4.9 */

	val = ((data->csc_mv[0] >> CSC_MATRIX_SHIFT) & 0x1FFF) |

		(((data->csc_mv[1] >> CSC_MATRIX_SHIFT) & 0x1FFF) << 16);

	val = ((data->csc_mv[0] >> shift_bit) & 0x1FFF) |

		(((data->csc_mv[1] >> shift_bit) & 0x1FFF) << 16);

	SDE_REG_WRITE(c, csc_reg_off, val);

	val = ((data->csc_mv[2] >> CSC_MATRIX_SHIFT) & 0x1FFF) |

		(((data->csc_mv[3] >> CSC_MATRIX_SHIFT) & 0x1FFF) << 16);

	val = ((data->csc_mv[2] >> shift_bit) & 0x1FFF) |

		(((data->csc_mv[3] >> shift_bit) & 0x1FFF) << 16);

	SDE_REG_WRITE(c, csc_reg_off + 0x4, val);

	val = ((data->csc_mv[4] >> CSC_MATRIX_SHIFT) & 0x1FFF) |

		(((data->csc_mv[5] >> CSC_MATRIX_SHIFT) & 0x1FFF) << 16);

	val = ((data->csc_mv[4] >> shift_bit) & 0x1FFF) |

		(((data->csc_mv[5] >> shift_bit) & 0x1FFF) << 16);

	SDE_REG_WRITE(c, csc_reg_off + 0x8, val);

	val = ((data->csc_mv[6] >> CSC_MATRIX_SHIFT) & 0x1FFF) |

		(((data->csc_mv[7] >> CSC_MATRIX_SHIFT) & 0x1FFF) << 16);

	val = ((data->csc_mv[6] >> shift_bit) & 0x1FFF) |

		(((data->csc_mv[7] >> shift_bit) & 0x1FFF) << 16);

	SDE_REG_WRITE(c, csc_reg_off + 0xc, val);

	val = (data->csc_mv[8] >> CSC_MATRIX_SHIFT) & 0x1FFF;

	val = (data->csc_mv[8] >> shift_bit) & 0x1FFF;

	SDE_REG_WRITE(c, csc_reg_off + 0x10, val);

}
@@ -407,7 +407,8 @@ void sde_hw_csc_setup(struct sde_hw_blk_reg_map *c, 
	if (!c || !data)

		return;



	sde_hw_csc_matrix_coeff_setup(c, csc_reg_off, data);

	/* matrix coeff - convert S15.16 to S4.9 */

	sde_hw_csc_matrix_coeff_setup(c, csc_reg_off, data, CSC_MATRIX_SHIFT);



	/* Pre clamp */

	val = (data->csc_pre_lv[0] << clamp_shift) | data->csc_pre_lv[1];

drivers/gpu/drm/msm/sde/sde_hw_util.h

+2 −1
Original line number Diff line number Diff line
@@ -189,7 +189,8 @@ u32 sde_hw_get_scaler3_ver(struct sde_hw_blk_reg_map *c, 
		u32 scaler_offset);



void sde_hw_csc_matrix_coeff_setup(struct sde_hw_blk_reg_map *c,

		u32 csc_reg_off, struct sde_csc_cfg *data);

		u32 csc_reg_off, struct sde_csc_cfg *data,

		u32 shift_bit);



void sde_hw_csc_setup(struct sde_hw_blk_reg_map  *c,

		u32 csc_reg_off,