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Commit 5ed33877 authored by Shengzhou Liu's avatar Shengzhou Liu Committed by Greg Kroah-Hartman
Browse files

powerpc/usb: remove checking PHY_CLK_VALID for UTMI PHY 



PHY_CLK_VALID bit doesn't work properly with UTMI PHY.
e.g. This bit is always zero on P5040, etc.
There is no need to check this bit for UTMI PHY, just keep
checking for ULPI PHY to prevent system hanging.

This patch should be squashed into previous commit 3735ba8d
"powerpc/usb: fix bug of CPU hang when missing USB PHY clock"

Signed-off-by: default avatarShengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 54575b05

drivers/usb/host/ehci-fsl.c

+1 −2
Original line number Diff line number Diff line
@@ -267,8 +267,7 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd, 
		break;

	}



	if ((pdata->controller_ver) && ((phy_mode == FSL_USB2_PHY_ULPI) ||

			(phy_mode == FSL_USB2_PHY_UTMI))) {

	if (pdata->controller_ver && (phy_mode == FSL_USB2_PHY_ULPI)) {

		/* check PHY_CLK_VALID to get phy clk valid */

		if (!spin_event_timeout(in_be32(non_ehci + FSL_SOC_USB_CTRL) &

				PHY_CLK_VALID, FSL_USB_PHY_CLK_TIMEOUT, 0)) {

include/linux/fsl_devices.h

+1 −1
Original line number Diff line number Diff line
@@ -19,7 +19,7 @@ 


#define FSL_UTMI_PHY_DLY	10	/*As per P1010RM, delay for UTMI

				PHY CLK to become stable - 10ms*/

#define FSL_USB_PHY_CLK_TIMEOUT	1000	/* uSec */

#define FSL_USB_PHY_CLK_TIMEOUT	10000	/* uSec */

#define FSL_USB_VER_OLD		0

#define FSL_USB_VER_1_6		1

#define FSL_USB_VER_2_2		2