Commit 5d58c620 authored Jun 26, 2015 by Zhen Lei Committed by Will Deacon Jul 08, 2015

iommu/arm-smmu: Fix the values of ARM64_TCR_{I,O}RGN0_SHIFT



The arm64 CPU architecture defines TCR[8:11] as holding the inner and
outer memory attributes for TTBR0.

This patch fixes the ARM SMMUv3 driver to pack these bits into the
context descriptor, rather than picking up the TTBR1 attributes as it
currently does.

Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>

parent d2e88e7c

drivers/iommu/arm-smmu-v3.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -269,10 +269,10 @@
		#define ARM64_TCR_TG0_SHIFT 14
		#define ARM64_TCR_TG0_MASK 0x3UL
		#define CTXDESC_CD_0_TCR_IRGN0_SHIFT 8
		#define ARM64_TCR_IRGN0_SHIFT 24
		#define ARM64_TCR_IRGN0_SHIFT 8
		#define ARM64_TCR_IRGN0_MASK 0x3UL
		#define CTXDESC_CD_0_TCR_ORGN0_SHIFT 10
		#define ARM64_TCR_ORGN0_SHIFT 26
		#define ARM64_TCR_ORGN0_SHIFT 10
		#define ARM64_TCR_ORGN0_MASK 0x3UL
		#define CTXDESC_CD_0_TCR_SH0_SHIFT 12
		#define ARM64_TCR_SH0_SHIFT 12