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Commit 5d54ddcb authored by Kumar Gala's avatar Kumar Gala
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[POWERPC] 85xx: Add basic Uniprocessor MPC8572 DS port 



Added basic board port for MPC8572 DS reference platform that is
similiar to the MPC8544/33 DS reference platform in uniprocessor mode.

Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
parent 26caeb2e

arch/powerpc/boot/dts/mpc8572ds.dts

0 → 100644
+404 −0
Original line number Diff line number Diff line 
/*

 * MPC8572 DS Device Tree Source

 *

 * Copyright 2007 Freescale Semiconductor Inc.

 *

 * This program is free software; you can redistribute  it and/or modify it

 * under  the terms of  the GNU General  Public License as published by the

 * Free Software Foundation;  either version 2 of the  License, or (at your

 * option) any later version.

 */



/ {

	model = "fsl,MPC8572DS";

	compatible = "fsl,MPC8572DS";

	#address-cells = <1>;

	#size-cells = <1>;



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		PowerPC,8572@0 {

			device_type = "cpu";

			reg = <0>;

			d-cache-line-size = <20>;	// 32 bytes

			i-cache-line-size = <20>;	// 32 bytes

			d-cache-size = <8000>;		// L1, 32K

			i-cache-size = <8000>;		// L1, 32K

			timebase-frequency = <0>;

			bus-frequency = <0>;

			clock-frequency = <0>;

		};

	};



	memory {

		device_type = "memory";

		reg = <00000000 00000000>;	// Filled by U-Boot

	};



	soc8572@ffe00000 {

		#address-cells = <1>;

		#size-cells = <1>;

		device_type = "soc";

		ranges = <00000000 ffe00000 00100000>;

		reg = <ffe00000 00001000>;	// CCSRBAR & soc regs, remove once parse code for immrbase fixed

		bus-frequency = <0>;		// Filled out by uboot.



		memory-controller@2000 {

			compatible = "fsl,mpc8572-memory-controller";

			reg = <2000 1000>;

			interrupt-parent = <&mpic>;

			interrupts = <12 2>;

		};



		memory-controller@6000 {

			compatible = "fsl,mpc8572-memory-controller";

			reg = <6000 1000>;

			interrupt-parent = <&mpic>;

			interrupts = <12 2>;

		};



		l2-cache-controller@20000 {

			compatible = "fsl,mpc8572-l2-cache-controller";

			reg = <20000 1000>;

			cache-line-size = <20>;	// 32 bytes

			cache-size = <80000>;	// L2, 512K

			interrupt-parent = <&mpic>;

			interrupts = <10 2>;

		};



		i2c@3000 {

			device_type = "i2c";

			compatible = "fsl-i2c";

			reg = <3000 100>;

			interrupts = <2b 2>;

			interrupt-parent = <&mpic>;

			dfsrr;

		};



		i2c@3100 {

			device_type = "i2c";

			compatible = "fsl-i2c";

			reg = <3100 100>;

			interrupts = <2b 2>;

			interrupt-parent = <&mpic>;

			dfsrr;

		};



		mdio@24520 {

			#address-cells = <1>;

			#size-cells = <0>;

			device_type = "mdio";

			compatible = "gianfar";

			reg = <24520 20>;

			phy0: ethernet-phy@0 {

				interrupt-parent = <&mpic>;

				interrupts = <a 1>;

				reg = <0>;

			};

			phy1: ethernet-phy@1 {

				interrupt-parent = <&mpic>;

				interrupts = <a 1>;

				reg = <1>;

			};

			phy2: ethernet-phy@2 {

				interrupt-parent = <&mpic>;

				interrupts = <a 1>;

				reg = <2>;

			};

			phy3: ethernet-phy@3 {

				interrupt-parent = <&mpic>;

				interrupts = <a 1>;

				reg = <3>;

			};

		};



		ethernet@24000 {

			#address-cells = <1>;

			#size-cells = <0>;

			device_type = "network";

			model = "eTSEC";

			compatible = "gianfar";

			reg = <24000 1000>;

			local-mac-address = [ 00 00 00 00 00 00 ];

			interrupts = <1d 2 1e 2 22 2>;

			interrupt-parent = <&mpic>;

			phy-handle = <&phy0>;

			phy-connection-type = "rgmii-id";

		};



		ethernet@25000 {

			#address-cells = <1>;

			#size-cells = <0>;

			device_type = "network";

			model = "eTSEC";

			compatible = "gianfar";

			reg = <25000 1000>;

			local-mac-address = [ 00 00 00 00 00 00 ];

			interrupts = <23 2 24 2 28 2>;

			interrupt-parent = <&mpic>;

			phy-handle = <&phy1>;

			phy-connection-type = "rgmii-id";

		};



		ethernet@26000 {

			#address-cells = <1>;

			#size-cells = <0>;

			device_type = "network";

			model = "eTSEC";

			compatible = "gianfar";

			reg = <26000 1000>;

			local-mac-address = [ 00 00 00 00 00 00 ];

			interrupts = <1f 2 20 2 21 2>;

			interrupt-parent = <&mpic>;

			phy-handle = <&phy2>;

			phy-connection-type = "rgmii-id";

		};



		ethernet@27000 {

			#address-cells = <1>;

			#size-cells = <0>;

			device_type = "network";

			model = "eTSEC";

			compatible = "gianfar";

			reg = <27000 1000>;

			local-mac-address = [ 00 00 00 00 00 00 ];

			interrupts = <25 2 26 2 27 2>;

			interrupt-parent = <&mpic>;

			phy-handle = <&phy3>;

			phy-connection-type = "rgmii-id";

		};



		serial@4500 {

			device_type = "serial";

			compatible = "ns16550";

			reg = <4500 100>;

			clock-frequency = <0>;

			interrupts = <2a 2>;

			interrupt-parent = <&mpic>;

		};



		serial@4600 {

			device_type = "serial";

			compatible = "ns16550";

			reg = <4600 100>;

			clock-frequency = <0>;

			interrupts = <2a 2>;

			interrupt-parent = <&mpic>;

		};



		global-utilities@e0000 {	//global utilities block

			compatible = "fsl,mpc8572-guts";

			reg = <e0000 1000>;

			fsl,has-rstcr;

		};



		mpic: pic@40000 {

			clock-frequency = <0>;

			interrupt-controller;

			#address-cells = <0>;

			#interrupt-cells = <2>;

			reg = <40000 40000>;

			compatible = "chrp,open-pic";

			device_type = "open-pic";

			big-endian;

		};

	};



	pcie@ffe08000 {

		compatible = "fsl,mpc8548-pcie";

		device_type = "pci";

		#interrupt-cells = <1>;

		#size-cells = <2>;

		#address-cells = <3>;

		reg = <ffe08000 1000>;

		bus-range = <0 ff>;

		ranges = <02000000 0 80000000 80000000 0 20000000

			  01000000 0 00000000 ffc00000 0 00010000>;

		clock-frequency = <1fca055>;

		interrupt-parent = <&mpic>;

		interrupts = <18 2>;

		interrupt-map-mask = <fb00 0 0 0>;

		interrupt-map = <

			/* IDSEL 0x11 - PCI slot 1 */

			8800 0 0 1 &mpic 2 1

			8800 0 0 2 &mpic 3 1

			8800 0 0 3 &mpic 4 1

			8800 0 0 4 &mpic 1 1



			/* IDSEL 0x12 - PCI slot 2 */

			9000 0 0 1 &mpic 3 1

			9000 0 0 2 &mpic 4 1

			9000 0 0 3 &mpic 1 1

			9000 0 0 4 &mpic 2 1



			// IDSEL 0x1c  USB

			e000 0 0 0 &i8259 c 2

			e100 0 0 0 &i8259 9 2

			e200 0 0 0 &i8259 a 2

			e300 0 0 0 &i8259 b 2



			// IDSEL 0x1d  Audio

			e800 0 0 0 &i8259 6 2



			// IDSEL 0x1e Legacy

			f000 0 0 0 &i8259 7 2

			f100 0 0 0 &i8259 7 2



			// IDSEL 0x1f IDE/SATA

			f800 0 0 0 &i8259 e 2

			f900 0 0 0 &i8259 5 2



			>;



		pcie@0 {

			reg = <0 0 0 0 0>;

			#size-cells = <2>;

			#address-cells = <3>;

			device_type = "pci";

			ranges = <02000000 0 80000000

				  02000000 0 80000000

				  0 20000000



				  01000000 0 00000000

				  01000000 0 00000000

				  0 00100000>;

			uli1575@0 {

				reg = <0 0 0 0 0>;

				#size-cells = <2>;

				#address-cells = <3>;

				ranges = <02000000 0 80000000

					  02000000 0 80000000

					  0 20000000



					  01000000 0 00000000

					  01000000 0 00000000

					  0 00100000>;

				isa@1e {

					device_type = "isa";

					#interrupt-cells = <2>;

					#size-cells = <1>;

					#address-cells = <2>;

					reg = <f000 0 0 0 0>;

					ranges = <1 0 01000000 0 0

						  00001000>;

					interrupt-parent = <&i8259>;



					i8259: interrupt-controller@20 {

						reg = <1 20 2

						       1 a0 2

						       1 4d0 2>;

						interrupt-controller;

						device_type = "interrupt-controller";

						#address-cells = <0>;

						#interrupt-cells = <2>;

						compatible = "chrp,iic";

						interrupts = <9 2>;

						interrupt-parent = <&mpic>;

					};



					i8042@60 {

						#size-cells = <0>;

						#address-cells = <1>;

						reg = <1 60 1 1 64 1>;

						interrupts = <1 3 c 3>;

						interrupt-parent =

							<&i8259>;



						keyboard@0 {

							reg = <0>;

							compatible = "pnpPNP,303";

						};



						mouse@1 {

							reg = <1>;

							compatible = "pnpPNP,f03";

						};

					};



					rtc@70 {

						compatible = "pnpPNP,b00";

						reg = <1 70 2>;

					};



					gpio@400 {

						reg = <1 400 80>;

					};

				};

			};

		};



	};



	pcie@ffe09000 {

		compatible = "fsl,mpc8548-pcie";

		device_type = "pci";

		#interrupt-cells = <1>;

		#size-cells = <2>;

		#address-cells = <3>;

		reg = <ffe09000 1000>;

		bus-range = <0 ff>;

		ranges = <02000000 0 a0000000 a0000000 0 20000000

			  01000000 0 00000000 ffc10000 0 00010000>;

		clock-frequency = <1fca055>;

		interrupt-parent = <&mpic>;

		interrupts = <1a 2>;

		interrupt-map-mask = <f800 0 0 7>;

		interrupt-map = <

			/* IDSEL 0x0 */

			0000 0 0 1 &mpic 4 1

			0000 0 0 2 &mpic 5 1

			0000 0 0 3 &mpic 6 1

			0000 0 0 4 &mpic 7 1

			>;

		pcie@0 {

			reg = <0 0 0 0 0>;

			#size-cells = <2>;

			#address-cells = <3>;

			device_type = "pci";

			ranges = <02000000 0 a0000000

				  02000000 0 a0000000

				  0 20000000



				  01000000 0 00000000

				  01000000 0 00000000

				  0 00100000>;

		};

	};



	pcie@ffe0a000 {

		compatible = "fsl,mpc8548-pcie";

		device_type = "pci";

		#interrupt-cells = <1>;

		#size-cells = <2>;

		#address-cells = <3>;

		reg = <ffe0a000 1000>;

		bus-range = <0 ff>;

		ranges = <02000000 0 c0000000 c0000000 0 20000000

			  01000000 0 00000000 ffc20000 0 00010000>;

		clock-frequency = <1fca055>;

		interrupt-parent = <&mpic>;

		interrupts = <1b 2>;

		interrupt-map = <

			/* IDSEL 0x0 */

			0000 0 0 1 &mpic 0 1

			0000 0 0 2 &mpic 1 1

			0000 0 0 3 &mpic 2 1

			0000 0 0 4 &mpic 3 1

			>;

		pcie@0 {

			reg = <0 0 0 0 0>;

			#size-cells = <2>;

			#address-cells = <3>;

			device_type = "pci";

			ranges = <02000000 0 c0000000

				  02000000 0 c0000000

				  0 20000000



				  01000000 0 00000000

				  01000000 0 00000000

				  0 00100000>;

		};

	};

};