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Commit 5ce81c22 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "drm/dp: Correctly mask DP_TRAINING_AUX_RD_INTERVAL values for DP 1.4"

parents 16d0ad0d 7113faeb

drivers/gpu/drm/drm_dp_helper.c

+18 −4
Original line number Diff line number Diff line
@@ -119,18 +119,32 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SI 
EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis);



void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) {

	if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)

	int rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &

			  DP_TRAINING_AUX_RD_MASK;



	if (rd_interval > 4)

		DRM_DEBUG_KMS("AUX interval %d, out of range (max 4)\n",

			      rd_interval);



	if (rd_interval == 0 || dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)

		udelay(100);

	else

		mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);

		mdelay(rd_interval * 4);

}

EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay);



void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) {

	if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)

	int rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &

			  DP_TRAINING_AUX_RD_MASK;



	if (rd_interval > 4)

		DRM_DEBUG_KMS("AUX interval %d, out of range (max 4)\n",

			      rd_interval);



	if (rd_interval == 0)

		udelay(400);

	else

		mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);

		mdelay(rd_interval * 4);

}

EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);

include/drm/drm_dp_helper.h

+1 −0
Original line number Diff line number Diff line
@@ -124,6 +124,7 @@ 
# define DP_DPCD_DISPLAY_CONTROL_CAPABLE     (1 << 3) /* edp v1.2 or higher */



#define DP_TRAINING_AUX_RD_INTERVAL         0x00e   /* XXX 1.2? */

# define DP_TRAINING_AUX_RD_MASK            0x7F    /* XXX 1.2? */



#define DP_ADAPTER_CAP			    0x00f   /* 1.2 */

# define DP_FORCE_LOAD_SENSE_CAP	    (1 << 0)