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Commit 5cbdcc2f authored by Huang, Xiong's avatar Huang, Xiong Committed by David S. Miller
Browse files

atl1c: clear bit MASTER_CTRL_CLK_SEL_DIS in atl1c_pcie_patch 



bit MASTER_CTRL_CLK_SEL_DIS could be set before enter suspend
clear it after resume to enable pclk(PCIE clock) switch to
low frequency(25M) in some circumstances to save power.

Signed-off-by: default avatarxiong <xiong@qca.qualcomm.com>
Tested-by: default avatarLiu David <dwliu@qca.qualcomm.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 7f5544d6

drivers/net/ethernet/atheros/atl1c/atl1c_main.c

+6 −1
Original line number Diff line number Diff line
@@ -80,7 +80,12 @@ static const u32 atl1c_default_msg = NETIF_MSG_DRV | NETIF_MSG_PROBE | 
	NETIF_MSG_LINK | NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP;

static void atl1c_pcie_patch(struct atl1c_hw *hw)

{

	u32 data;

	u32 mst_data, data;



	/* pclk sel could switch to 25M */

	AT_READ_REG(hw, REG_MASTER_CTRL, &mst_data);

	mst_data &= ~MASTER_CTRL_CLK_SEL_DIS;

	AT_WRITE_REG(hw, REG_MASTER_CTRL, mst_data);



	AT_READ_REG(hw, REG_PCIE_PHYMISC, &data);

	data |= PCIE_PHYMISC_FORCE_RCV_DET;