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Commit 5c2b0a85 authored by Tony Prisk's avatar Tony Prisk
Browse files

dts: vt8500: Populate missing PLL nodes 



Add the missing devicetree nodes for PLL's found on the WM8505, WM8650
and WM8850 SoCs.

Signed-off-by: default avatarTony Prisk <linux@prisktech.co.nz>
parent 7d4c6f3c

arch/arm/boot/dts/wm8505.dtsi

+21 −0
Original line number Diff line number Diff line
@@ -81,6 +81,13 @@ 
					clock-frequency = <25000000>;

				};



				plla: plla {

					#clock-cells = <0>;

					compatible = "via,vt8500-pll-clock";

					clocks = <&ref25>;

					reg = <0x200>;

				};



				pllb: pllb {

					#clock-cells = <0>;

					compatible = "via,vt8500-pll-clock";
@@ -88,6 +95,20 @@ 
					reg = <0x204>;

				};



				pllc: pllc {

					#clock-cells = <0>;

					compatible = "via,vt8500-pll-clock";

					clocks = <&ref25>;

					reg = <0x208>;

				};



				plld: plld {

					#clock-cells = <0>;

					compatible = "via,vt8500-pll-clock";

					clocks = <&ref25>;

					reg = <0x20c>;

				};



				clkuart0: uart0 {

					#clock-cells = <0>;

					compatible = "via,vt8500-device-clock";

arch/arm/boot/dts/wm8650.dtsi

+21 −0
Original line number Diff line number Diff line
@@ -92,6 +92,27 @@ 
					reg = <0x204>;

				};



				pllc: pllc {

					#clock-cells = <0>;

					compatible = "wm,wm8650-pll-clock";

					clocks = <&ref25>;

					reg = <0x208>;

				};



				plld: plld {

					#clock-cells = <0>;

					compatible = "wm,wm8650-pll-clock";

					clocks = <&ref25>;

					reg = <0x20c>;

				};



				plle: plle {

					#clock-cells = <0>;

					compatible = "wm,wm8650-pll-clock";

					clocks = <&ref25>;

					reg = <0x210>;

				};



				clkuart0: uart0 {

 					#clock-cells = <0>;

 					compatible = "via,vt8500-device-clock";

arch/arm/boot/dts/wm8850.dtsi

+35 −0
Original line number Diff line number Diff line
@@ -95,6 +95,41 @@ 
					reg = <0x204>;

				};



				pllc: pllc {

					#clock-cells = <0>;

					compatible = "wm,wm8850-pll-clock";

					clocks = <&ref25>;

					reg = <0x208>;

				};



				plld: plld {

					#clock-cells = <0>;

					compatible = "wm,wm8850-pll-clock";

					clocks = <&ref25>;

					reg = <0x20c>;

				};



				plle: plle {

					#clock-cells = <0>;

					compatible = "wm,wm8850-pll-clock";

					clocks = <&ref25>;

					reg = <0x210>;

				};



				pllf: pllf {

					#clock-cells = <0>;

					compatible = "wm,wm8850-pll-clock";

					clocks = <&ref25>;

					reg = <0x214>;

				};



				pllg: pllg {

					#clock-cells = <0>;

					compatible = "wm,wm8850-pll-clock";

					clocks = <&ref25>;

					reg = <0x218>;

				};



				clkuart0: uart0 {

					#clock-cells = <0>;

					compatible = "via,vt8500-device-clock";