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Commit 5bd9be0b authored by Skylar Chang's avatar Skylar Chang
Browse files

msm: ipa3: checking gsi intset value on clk-vote 



Add the check on gsi INTSET value with IPA clk-voting
also read the markers where ipa-uc to put on mail-box
17. Mapped G_RD_CNTR register in uc-cb as well.

Change-Id: I57e341bf2c46402c1f895f16ce0ad840c69b2013
Signed-off-by: default avatarSkylar Chang <chiaweic@codeaurora.org>
parent 9cd5740f

drivers/platform/msm/gsi/gsi.c

+11 −0
Original line number Diff line number Diff line
@@ -4020,6 +4020,17 @@ int gsi_alloc_channel_ee(unsigned int chan_idx, unsigned int ee, int *code) 
}

EXPORT_SYMBOL(gsi_alloc_channel_ee);





int gsi_chk_intset_value(void)

{

	uint32_t val;



	val = gsi_readl(gsi_ctx->base +

		GSI_EE_n_CNTXT_INTSET_OFFS(gsi_ctx->per.ee));

	return val;

}

EXPORT_SYMBOL(gsi_chk_intset_value);



int gsi_map_virtual_ch_to_per_ep(u32 ee, u32 chan_num, u32 per_ep_index)

{

	if (!gsi_ctx) {

drivers/platform/msm/ipa/ipa_v3/ipa.c

+29 −0
Original line number Diff line number Diff line
@@ -3879,6 +3879,15 @@ void ipa3_inc_client_enable_clks(struct ipa_active_client_logging_info *id) 
	IPADBG_LOW("active clients = %d\n",

		atomic_read(&ipa3_ctx->ipa3_active_clients.cnt));

	ipa3_suspend_apps_pipes(false);

	if (!ipa3_uc_state_check() &&

		(ipa3_ctx->ipa_hw_type >= IPA_HW_v4_1)) {

		ipa3_read_mailbox_17(IPA_PC_RESTORE_CONTEXT_STATUS_SUCCESS);

		/* assert if intset = 0 */

		if (ipa3_ctx->gsi_chk_intset_value == 0) {

			IPAERR("expected 1, value: 0\n");

			ipa_assert();

		}

	}

	mutex_unlock(&ipa3_ctx->ipa3_active_clients.mutex);

}
@@ -5297,6 +5306,8 @@ static int ipa3_pre_init(const struct ipa3_plat_drv_res *resource_p, 
	ipa3_ctx->ipa_config_is_mhi = resource_p->ipa_mhi_dynamic_config;

	ipa3_ctx->mhi_evid_limits[0] = resource_p->mhi_evid_limits[0];

	ipa3_ctx->mhi_evid_limits[1] = resource_p->mhi_evid_limits[1];

	ipa3_ctx->uc_mailbox17_chk = 0;

	ipa3_ctx->uc_mailbox17_mismatch = 0;



	WARN(ipa3_ctx->ipa3_hw_mode != IPA_HW_MODE_NORMAL,

		"Non NORMAL IPA HW mode, is this emulation platform ?");
@@ -6329,6 +6340,12 @@ static int ipa_smmu_uc_cb_probe(struct device *dev) 
	int fast = 1;

	int ret;

	u32 iova_ap_mapping[2];

	/* G_RD_CNTR register */

	u32 a1 = 0x0C220000;

	u32 a2 = 0x4000;

	unsigned long iova_p;

	phys_addr_t pa_p;

	u32 size_p;



	IPADBG("UC CB PROBE sub pdev=%pK\n", dev);
@@ -6429,6 +6446,18 @@ static int ipa_smmu_uc_cb_probe(struct device *dev) 
		return ret;

	}



	/* map G_RD_CNTR for uc*/

	IPA_SMMU_ROUND_TO_PAGE(a1, a1, a2,

		iova_p, pa_p, size_p);



	if (ipa3_ctx->ipa_hw_type == IPA_HW_v4_1) {

		IPADBG("mapping 0x%lx to 0x%pa size %d\n",

			iova_p, &pa_p, size_p);

		ipa3_iommu_map(cb->mapping->domain,

			iova_p, pa_p, size_p,

			IOMMU_READ | IOMMU_WRITE | IOMMU_MMIO);

	}



	cb->next_addr = cb->va_end;

	ipa3_ctx->uc_pdev = dev;

drivers/platform/msm/ipa/ipa_v3/ipa_i.h

+23 −0
Original line number Diff line number Diff line
@@ -80,6 +80,16 @@ 


#define NAPI_WEIGHT 60



/* Bit pattern for SW to identify in middle of PC saving */

#define PC_SAVE_CONTEXT_SAVE_ENTERED            0xDEAFDEAF

/* Bit pattern for SW to identify that PC saving completed */

#define PC_SAVE_CONTEXT_STATUS_SUCCESS          0xFADEFADE

/* Bit pattern for SW to identify PC restoration is ongoing */

#define PC_RESTORE_CONTEXT_ENTERED              0xFACEFACE

/*Bit pattern for SW to identify PC restoration completed */

#define PC_RESTORE_CONTEXT_STATUS_SUCCESS       0xCAFECAFE





#define IPADBG(fmt, args...) \

	do { \

		pr_debug(DRV_NAME " %s:%d " fmt, __func__, __LINE__, ## args);\
@@ -847,6 +857,13 @@ enum ipa3_sys_pipe_policy { 
	IPA_POLICY_INTR_POLL_MODE,

};



enum uc_state {

	IPA_PC_SAVE_CONTEXT_SAVE_ENTERED,

	IPA_PC_SAVE_CONTEXT_STATUS_SUCCESS,

	IPA_PC_RESTORE_CONTEXT_ENTERED,

	IPA_PC_RESTORE_CONTEXT_STATUS_SUCCESS,

};



struct ipa3_repl_ctx {

	struct ipa3_rx_pkt_wrapper **cache;

	atomic_t head_idx;
@@ -1672,6 +1689,9 @@ struct ipa3_context { 
	struct mbox_client mbox_client;

	struct mbox_chan *mbox;

	atomic_t ipa_clk_vote;

	int gsi_chk_intset_value;

	int uc_mailbox17_chk;

	int uc_mailbox17_mismatch;

};



struct ipa3_plat_drv_res {
@@ -2527,6 +2547,7 @@ int ipa3_uc_interface_init(void); 
int ipa3_uc_is_gsi_channel_empty(enum ipa_client_type ipa_client);

int ipa3_uc_state_check(void);

int ipa3_uc_loaded_check(void);

void ipa3_uc_map_cntr_reg_notify(void);

int ipa3_uc_register_ready_cb(struct notifier_block *nb);

int ipa3_uc_unregister_ready_cb(struct notifier_block *nb);

int ipa3_uc_send_cmd(u32 cmd, u32 opcode, u32 expected_status,
@@ -2682,6 +2703,8 @@ int ipa3_ntn_init(void); 
int ipa3_get_ntn_stats(struct Ipa3HwStatsNTNInfoData_t *stats);

struct dentry *ipa_debugfs_get_root(void);

bool ipa3_is_msm_device(void);

void ipa3_read_mailbox_17(enum uc_state state);



struct device *ipa3_get_pdev(void);

void ipa3_enable_dcd(void);

void ipa3_disable_prefetch(enum ipa_client_type client);

drivers/platform/msm/ipa/ipa_v3/ipa_qmi_service.c

+7 −0
Original line number Diff line number Diff line
@@ -243,6 +243,9 @@ static void ipa3_handle_modem_init_cmplt_req(struct qmi_handle *qmi_handle, 


	if (ipa3_modem_init_cmplt == false) {

		ipa3_modem_init_cmplt = true;

		if ((ipa3_qmi_modem_init_fin == true) &&

			(ipa3_ctx->ipa_hw_type == IPA_HW_v4_1))

			ipa3_uc_map_cntr_reg_notify();

	}



	memset(&resp, 0, sizeof(resp));
@@ -1120,6 +1123,10 @@ static void ipa3_q6_clnt_svc_arrive(struct work_struct *work) 


	ipa3_qmi_modem_init_fin = true;



	if ((ipa3_modem_init_cmplt == true) &&

		(ipa3_ctx->ipa_hw_type == IPA_HW_v4_1))

		ipa3_uc_map_cntr_reg_notify();



	/* In cold-bootup, first_time_handshake = false */

	ipa3_q6_handshake_complete(first_time_handshake);

	first_time_handshake = true;

drivers/platform/msm/ipa/ipa_v3/ipa_uc.c

+9 −0
Original line number Diff line number Diff line
@@ -539,6 +539,15 @@ static void ipa3_uc_wigig_misc_int_handler(enum ipa_irq_type interrupt, 
	IPADBG("exit\n");

}



void ipa3_uc_map_cntr_reg_notify(void)

{

	IPAWANDBG("complete the mapping of G_RD_CNTR register\n");

	ipa3_uc_send_cmd(0,

		IPA_CPU_2_HW_CMD_DEBUG_GET_INFO,

		IPA_HW_2_CPU_RESPONSE_CMD_COMPLETED,

		false, 0);

}



static int ipa3_uc_send_cmd_64b_param(u32 cmd_lo, u32 cmd_hi, u32 opcode,

	u32 expected_status, bool polling_mode, unsigned long timeout_jiffies)

{