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Commit 5b31b8b1 authored by Can Guo's avatar Can Guo
Browse files

phy: qcom-ufs: Update UFS PHY power up sequence 



Updated the UFS PHY power up sequence per the updated PHY Hardware
Programming Guide.

Change-Id: I6420825a177171534e8c10c2680207b6c1872705
Signed-off-by: default avatarCan Guo <cang@codeaurora.org>
parent 71644d76

drivers/phy/qualcomm/phy-qcom-ufs-qmp-v4.c

+11 −1
Original line number Diff line number Diff line
@@ -35,9 +35,19 @@ int ufs_qcom_phy_qmp_v4_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy, 
	 */

	ufs_qcom_phy_write_tbl(ufs_qcom_phy, phy_cal_table_rate_A,

			       ARRAY_SIZE(phy_cal_table_rate_A));

	if (ufs_qcom_phy->lanes_per_direction == 2)

	if ((major == 0x4) && (minor == 0x001) && (step == 0x0000))

		ufs_qcom_phy_write_tbl(ufs_qcom_phy, phy_cal_table_rate_A_v2,

				       ARRAY_SIZE(phy_cal_table_rate_A_v2));



	if (ufs_qcom_phy->lanes_per_direction == 2) {

		ufs_qcom_phy_write_tbl(ufs_qcom_phy, phy_cal_table_2nd_lane,

				       ARRAY_SIZE(phy_cal_table_2nd_lane));

		if ((major == 0x4) && (minor == 0x001) && (step == 0x0000))

			ufs_qcom_phy_write_tbl(ufs_qcom_phy,

					phy_cal_table_2nd_lane_v2,

					ARRAY_SIZE(phy_cal_table_2nd_lane_v2));

	}



	if (is_rate_B)

		ufs_qcom_phy_write_tbl(ufs_qcom_phy, phy_cal_table_rate_B,

				       ARRAY_SIZE(phy_cal_table_rate_B));

drivers/phy/qualcomm/phy-qcom-ufs-qmp-v4.h

+20 −0
Original line number Diff line number Diff line
@@ -263,6 +263,16 @@ static struct ufs_qcom_phy_calibration phy_cal_table_rate_A[] = { 
	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SO_GAIN, 0x04),

};



static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_v2[] = {

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_LANE_MODE_1, 0x35),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x5A),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FO_GAIN, 0x0E),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_LOW, 0x6D),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_HIGH, 0x6D),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_HIGH2, 0xED),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_HIGH4, 0x3C),

};



static struct ufs_qcom_phy_calibration phy_cal_table_2nd_lane[] = {

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
@@ -307,6 +317,16 @@ static struct ufs_qcom_phy_calibration phy_cal_table_2nd_lane[] = { 
	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_SO_GAIN, 0x04),

};



static struct ufs_qcom_phy_calibration phy_cal_table_2nd_lane_v2[] = {

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_LANE_MODE_1, 0x35),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_SO_SATURATION_AND_ENABLE, 0x5A),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FO_GAIN, 0x0E),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_LOW, 0x6D),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_HIGH, 0x6D),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_HIGH2, 0xED),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_HIGH4, 0x3C),

};



static struct ufs_qcom_phy_calibration phy_cal_table_rate_B[] = {

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x06),

};