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Commit 5b163fe8 authored by Taniya Das's avatar Taniya Das Committed by Gerrit - the friendly Code Review server
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clk: smd-rpm: Add support for QPIC & CE1 clock for QCS405 



QPIC & CE clocks are required to be voted from the clients, so add the
relevant clock ids for the same.
Remove the clock ids and clock handles which are no longer required on this
target.

Change-Id: If2edbb4526230b3c1f6d929f6bf0dafa0b800e95
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent d732694b

drivers/clk/qcom/clk-smd-rpm.c

+16 −17
Original line number Diff line number Diff line
@@ -519,7 +519,7 @@ static struct clk_hw *msm8916_clks[] = { 


static const struct rpm_smd_clk_desc rpm_clk_msm8916 = {

	.clks = msm8916_clks,

	.num_rpm_clks = RPM_RF_CLK2_A_PIN,

	.num_rpm_clks = RPM_SMD_RF_CLK2_A_PIN,

	.num_clks = ARRAY_SIZE(msm8916_clks),

};
@@ -600,14 +600,11 @@ DEFINE_CLK_SMD_RPM_BRANCH(qcs405, cxo, cxo_a, QCOM_SMD_RPM_MISC_CLK, 0, 
								19200000);

DEFINE_CLK_SMD_RPM(qcs405, pnoc_clk, pnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);

DEFINE_CLK_SMD_RPM(qcs405, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);

DEFINE_CLK_SMD_RPM(qcs405, bimc_gpu_clk, bimc_gpu_a_clk,

						QCOM_SMD_RPM_MEM_CLK, 2);

DEFINE_CLK_SMD_RPM(qcs405, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);

DEFINE_CLK_SMD_RPM(qcs405, sysmmnoc_clk, sysmmnoc_clk_a_clk,

						QCOM_SMD_RPM_BUS_CLK, 2);

DEFINE_CLK_SMD_RPM(qcs405, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0);

DEFINE_CLK_SMD_RPM_QDSS(qcs405, qdss_clk, qdss_a_clk,

						QCOM_SMD_RPM_MISC_CLK, 1);

DEFINE_CLK_SMD_RPM(qcs405, qpic_clk, qpic_a_clk, QCOM_SMD_RPM_QPIC_CLK, 0);

DEFINE_CLK_SMD_RPM(qcs405, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0);



/* SMD_XO_BUFFER */

DEFINE_CLK_SMD_RPM_XO_BUFFER(qcs405, bb_clk1, bb_clk1_a, 1);
@@ -620,12 +617,10 @@ DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(qcs405, bb_clk2_pin, bb_clk2_a_pin, 2); 
/* Voter clocks */

static DEFINE_CLK_VOTER(pnoc_msmbus_clk, pnoc_clk, LONG_MAX);

static DEFINE_CLK_VOTER(snoc_msmbus_clk, snoc_clk, LONG_MAX);

static DEFINE_CLK_VOTER(sysmmnoc_msmbus_clk, sysmmnoc_clk,  LONG_MAX);

static DEFINE_CLK_VOTER(bimc_msmbus_clk, bimc_clk, LONG_MAX);



static DEFINE_CLK_VOTER(pnoc_msmbus_a_clk, pnoc_a_clk, LONG_MAX);

static DEFINE_CLK_VOTER(snoc_msmbus_a_clk, snoc_a_clk, LONG_MAX);

static DEFINE_CLK_VOTER(sysmmnoc_msmbus_a_clk, sysmmnoc_a_clk,  LONG_MAX);

static DEFINE_CLK_VOTER(bimc_msmbus_a_clk, bimc_a_clk, LONG_MAX);

static DEFINE_CLK_VOTER(pnoc_keepalive_a_clk, pnoc_a_clk, LONG_MAX);
@@ -640,8 +635,13 @@ static DEFINE_CLK_VOTER(bimc_usb_clk, bimc_clk, LONG_MAX); 
static DEFINE_CLK_VOTER(snoc_wcnss_a_clk, snoc_a_clk, LONG_MAX);

static DEFINE_CLK_VOTER(bimc_wcnss_a_clk, bimc_a_clk, LONG_MAX);



static DEFINE_CLK_VOTER(mcd_ce1_clk, ce1_clk, 85710000);

static DEFINE_CLK_VOTER(qcedev_ce1_clk, ce1_clk, 85710000);

static DEFINE_CLK_VOTER(qcrypto_ce1_clk, ce1_clk, 85710000);

static DEFINE_CLK_VOTER(qseecom_ce1_clk, ce1_clk, 85710000);

static DEFINE_CLK_VOTER(scm_ce1_clk, ce1_clk, 85710000);



/* Branch Voter clocks */

static DEFINE_CLK_BRANCH_VOTER(cxo_gcc, cxo);

static DEFINE_CLK_BRANCH_VOTER(cxo_otg_clk, cxo);

static DEFINE_CLK_BRANCH_VOTER(cxo_lpm_clk, cxo);

static DEFINE_CLK_BRANCH_VOTER(cxo_pil_pronto_clk, cxo);
@@ -672,12 +672,8 @@ static struct clk_hw *qcs405_clks[] = { 
	[RPM_SMD_DIV_A_CLK2]		= &qcs405_div_clk2_a.hw,

	[RPM_SMD_PNOC_CLK]		= &qcs405_pnoc_clk.hw,

	[RPM_SMD_PNOC_A_CLK]		= &qcs405_pnoc_a_clk.hw,

	[RPM_SMD_IPA_CLK]		= &qcs405_ipa_clk.hw,

	[RPM_SMD_IPA_A_CLK]		= &qcs405_ipa_a_clk.hw,

	[RPM_SMD_BIMC_GPU_CLK]		= &qcs405_bimc_gpu_clk.hw,

	[RPM_SMD_BIMC_GPU_A_CLK]	= &qcs405_bimc_gpu_a_clk.hw,

	[RPM_SMD_SYSMMNOC_CLK]		= &qcs405_sysmmnoc_clk.hw,

	[RPM_SMD_SYSMMNOC_A_CLK]	= &qcs405_sysmmnoc_a_clk.hw,

	[RPM_SMD_QPIC_CLK]		= &qcs405_qpic_clk.hw,

	[RPM_SMD_QPIC_A_CLK]		= &qcs405_qpic_a_clk.hw,

	[PNOC_MSMBUS_CLK]		= &pnoc_msmbus_clk.hw,

	[PNOC_MSMBUS_A_CLK]		= &pnoc_msmbus_a_clk.hw,

	[PNOC_KEEPALIVE_A_CLK]		= &pnoc_keepalive_a_clk.hw,
@@ -685,8 +681,6 @@ static struct clk_hw *qcs405_clks[] = { 
	[SNOC_MSMBUS_A_CLK]		= &snoc_msmbus_a_clk.hw,

	[BIMC_MSMBUS_CLK]		= &bimc_msmbus_clk.hw,

	[BIMC_MSMBUS_A_CLK]		= &bimc_msmbus_a_clk.hw,

	[SYSMMNOC_MSMBUS_CLK]		= &sysmmnoc_msmbus_clk.hw,

	[SYSMMNOC_MSMBUS_A_CLK]		= &sysmmnoc_msmbus_a_clk.hw,

	[PNOC_USB_CLK]			= &pnoc_usb_clk.hw,

	[PNOC_USB_A_CLK]		= &pnoc_usb_a_clk.hw,

	[SNOC_USB_CLK]			= &snoc_usb_clk.hw,
@@ -695,6 +689,11 @@ static struct clk_hw *qcs405_clks[] = { 
	[BIMC_USB_A_CLK]		= &bimc_usb_a_clk.hw,

	[SNOC_WCNSS_A_CLK]		= &snoc_wcnss_a_clk.hw,

	[BIMC_WCNSS_A_CLK]		= &bimc_wcnss_a_clk.hw,

	[MCD_CE1_CLK]			= &mcd_ce1_clk.hw,

	[QCEDEV_CE1_CLK]		= &qcedev_ce1_clk.hw,

	[QCRYPTO_CE1_CLK]		= &qcrypto_ce1_clk.hw,

	[QSEECOM_CE1_CLK]		= &qseecom_ce1_clk.hw,

	[SCM_CE1_CLK]			= &scm_ce1_clk.hw,

	[CXO_SMD_OTG_CLK]		= &cxo_otg_clk.hw,

	[CXO_SMD_LPM_CLK]		= &cxo_otg_clk.hw,

	[CXO_SMD_PIL_PRONTO_CLK]	= &cxo_pil_pronto_clk.hw,

include/dt-bindings/clock/qcom,rpmcc.h

+15 −14
Original line number Diff line number Diff line
@@ -101,12 +101,10 @@ 
#define RPM_SMD_CXO_A1_A_PIN			59

#define RPM_SMD_CXO_A2_PIN			60

#define RPM_SMD_CXO_A2_A_PIN			61

#define RPM_SMD_IPA_CLK				62

#define RPM_SMD_IPA_A_CLK			63

#define RPM_SMD_BIMC_GPU_CLK			64

#define RPM_SMD_BIMC_GPU_A_CLK			65

#define RPM_SMD_SYSMMNOC_CLK			66

#define RPM_SMD_SYSMMNOC_A_CLK			67

#define RPM_SMD_QPIC_CLK			64

#define RPM_SMD_QPIC_A_CLK			65

#define RPM_SMD_CE1_CLK				66

#define RPM_SMD_CE1_A_CLK			67

#define PNOC_MSMBUS_CLK				68

#define PNOC_MSMBUS_A_CLK			69

#define PNOC_KEEPALIVE_A_CLK			70
@@ -114,8 +112,6 @@ 
#define SNOC_MSMBUS_A_CLK			72

#define BIMC_MSMBUS_CLK				73

#define BIMC_MSMBUS_A_CLK			74

#define SYSMMNOC_MSMBUS_CLK			75

#define SYSMMNOC_MSMBUS_A_CLK			76

#define PNOC_USB_CLK				77

#define PNOC_USB_A_CLK				78

#define SNOC_USB_CLK				79
@@ -124,11 +120,16 @@ 
#define BIMC_USB_A_CLK				82

#define SNOC_WCNSS_A_CLK			83

#define BIMC_WCNSS_A_CLK			84

#define CXO_SMD_OTG_CLK				85

#define CXO_SMD_LPM_CLK				86

#define CXO_SMD_PIL_PRONTO_CLK			87

#define CXO_SMD_PIL_MSS_CLK			88

#define CXO_SMD_WLAN_CLK			89

#define CXO_SMD_PIL_LPASS_CLK			90

#define MCD_CE1_CLK				85

#define QCEDEV_CE1_CLK				86

#define QCRYPTO_CE1_CLK				87

#define QSEECOM_CE1_CLK				88

#define SCM_CE1_CLK				89

#define CXO_SMD_OTG_CLK				90

#define CXO_SMD_LPM_CLK				91

#define CXO_SMD_PIL_PRONTO_CLK			92

#define CXO_SMD_PIL_MSS_CLK			93

#define CXO_SMD_WLAN_CLK			94

#define CXO_SMD_PIL_LPASS_CLK			95



#endif

include/linux/soc/qcom/smd-rpm.h

+1 −0
Original line number Diff line number Diff line
@@ -27,6 +27,7 @@ struct qcom_smd_rpm; 
#define QCOM_SMD_RPM_SMPB	0x62706d73

#define QCOM_SMD_RPM_SPDM	0x63707362

#define QCOM_SMD_RPM_VSA	0x00617376

#define QCOM_SMD_RPM_CE_CLK	0x00006563



int qcom_rpm_smd_write(struct qcom_smd_rpm *rpm,

		       int state,