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Commit 5adf0b88 authored by Subhash Jadavani's avatar Subhash Jadavani Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: add UFS clocks for SDM855 



Now that clock driver is enabled, all the UFS clocks are added.

Change-Id: I5d69384f9aebf22501f568338431fc469574f833
Signed-off-by: default avatarSubhash Jadavani <subhashj@codeaurora.org>
parent 28bb5f16

arch/arm64/boot/dts/qcom/sdm855.dtsi

+25 −0
Original line number Diff line number Diff line
@@ -1218,6 +1218,13 @@ 


		lanes-per-direction = <2>;



		clock-names = "ref_clk_src",

			"ref_clk",

			"ref_aux_clk";

		clocks = <&clock_rpmh RPMH_CXO_CLK>,

			<&clock_gcc GCC_UFS_MEM_CLKREF_CLK>,

			<&clock_gcc GCC_UFS_PHY_PHY_AUX_CLK>;



		status = "disabled";

	};
@@ -1232,14 +1239,32 @@ 
		dev-ref-clk-freq = <0>; /* 19.2 MHz */



		clock-names =

			"core_clk",

			"bus_aggr_clk",

			"iface_clk",

			"core_clk_unipro",

			"core_clk_ice",

			"ref_clk",

			"tx_lane0_sync_clk",

			"rx_lane0_sync_clk",

			"rx_lane1_sync_clk";

		clocks =

			<&clock_gcc GCC_UFS_PHY_AXI_CLK>,

			<&clock_gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,

			<&clock_gcc GCC_UFS_PHY_AHB_CLK>,

			<&clock_gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,

			<&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>,

			<&clock_rpmh RPMH_CXO_CLK>,

			<&clock_gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,

			<&clock_gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,

			<&clock_gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;

		freq-table-hz =

			<50000000 200000000>,

			<0 0>,

			<0 0>,

			<37500000 150000000>,

			<75000000 300000000>,

			<0 0>,

			<0 0>,

			<0 0>,

			<0 0>;