Loading Documentation/devicetree/bindings/arm/msm/rpm_master_stats.txt 0 → 100644 +47 −0 Original line number Diff line number Diff line * RPM Stats RPM maintains a counter of the masters i.e APPS, MPPS etc number of times the SoC entered a deeper sleep mode involving lowering or powering down the backbone rails - Cx and Mx and the oscillator clock, XO. PROPERTIES - compatible: Usage: required Value type: <string> Definition: Should be "qcom,rpm-master-stats". - reg: Usage: required Value type: <prop-encoded-array> Definition: The address on the RPM RAM from where the stats are read should be provided as "phys_addr_base". The offset from which the stats are available should be provided as "offset_addr". - reg-names: Usage: required Value type: <prop-encoded-array> Definition: Provides labels for the reg property. - qcom,masters: Usage: required Value tye: <string list> Defination: Provides the masters list. qcom,master-offset: Usage: required Value tye: <prop-encoded-array> Defination: Provides the masters list EXAMPLE: qcom,rpm-master-stats@60150 { compatible = "qcom,rpm-master-stats"; reg = <0x60150 0x5000>; qcom,masters = "APSS", "MPSS", "PRONTO", "TZ", "LPASS"; qcom,master-stats-version = <2>; qcom,master-offset = <4096>; }; Documentation/devicetree/bindings/arm/msm/spm-v2.txt 0 → 100644 +169 −0 Original line number Diff line number Diff line * MSM Subsystem Power Manager (spm-v2) S4 generation of MSMs have SPM hardware blocks to control the Application Processor Sub-System power. These SPM blocks run individual state machine to determine what the core (L2 or Krait/Scorpion) would do when the WFI instruction is executed by the core. The SAW hardware block handles SPM and AVS functionality for the cores. The devicetree representation of the SPM block should be: Required properties - compatible: "qcom,spm-v2" - reg: The physical address and the size of the SPM's memory mapped registers - qcom,cpu: phandle for the CPU that the SPM block is attached to. This field is required on only for SPMs that control the CPU. This field is not required for SPMs that control L2/CCI/L3 - qcom,saw2-ver-reg: The location of the version register - qcom,name: The name with which a SPM device is identified by the power management code. ---------------------------------------------------- Non-PSCI targets should follow the rules shown below ---------------------------------------------------- Required properties for only Non-PSCI targets: - qcom,saw2-cfg: SAW2 configuration register - qcom,saw2-spm-ctl: The SPM control register - qcom,saw2-spm-dly: Provides the values for the SPM delay command in the SPM sequence Optional properties for only Non-PSCI targets - reg-names: Register names for the physical address required if spm device has more than one physical addressed to be mapped. Allowed register names are: "saw-base", "q2s", "hw-flush", "slpreq" - qcom,saw2-avs-ctl: The AVS control register - qcom,saw2-avs-hysterisis: The AVS hysterisis register to delay the AVS controller requests - qcom,vctl-timeout-us: The timeout value in us to wait for voltage to change after sending the voltage command to the PMIC - qcom,saw2-avs-limit: The AVS limit register - qcom,saw2-avs-dly: The AVS delay register is used to specify the delay values between AVS controller requests - qcom,saw2-pmic-data0..7: Specify the pmic data value and the associated FTS index to send the PMIC data to - qcom,vctl-port: The PVC (PMIC Virtual Channel) port used for changing voltage - qcom,phase-port: The PVC port used for changing the number of phases - qcom,pfm-port: The PVC port used for enabling PWM/PFM modes - qcom,cpu-vctl-mask: Mask of cpus, whose voltage the spm device can control. Depricated: Replaced with cpu-vctl-list when cpu phandles are available. - qcom,cpu-vctl-list: List of cpu node phandles, whose voltage the spm device can control. - qcom,use-qchannel-for-pc: Boolean property to specify if qchannel should be ignored when entering power collapse. If this property is set qchannel will not be ignored in power collapse. - qcom,supports-rpm-hs: Indicates that this SPM instance allow handshake with RPM processor when executing the sleep command in the SPM sequence. Supported only on SAW2 v3.0 and above. - qcom,use-spm-clock-gating: This boolean property is used to indicate that the SPM needs to be used for clock gating. Using the SPM for clock gating would result in auto clock gating being disabled. Use this on targets that do not support or do not use auto clock gating. - qcom,use-qchannel-for-wfi: This boolean property is used to indicate that the SPM gets triggerd by the qchannel and not by means of wfi. So a wfe could trigger a spm for clock gating as well. - modes: Lists all the available low power modes for the device Second level properties for modes Required properties (if modes node is available) - qcom,label: Specifies the mode name such as: qcom,saw2-spm-cmd-wfi: WFI mode qcom,saw2-spm-cmd-ret: Retention mode qcom,saw2-spm-cmd-spc: Standalone PC mode qcom,saw2-spm-cmd-pc: Power Collapse mode qcom,saw2-spm-cmd-gdhs: GDHS mode - qcom,sequence: Specifies sequence for the low power mode Optional properties - qcom,pc_mode: Specifies pc_mode bit should be set in the SPM control register - qcom,ret_mode: Specifies ret_mode bit should be set in the SPM control register - qcom,spm_en: Specifies spm_en bit should be set in the SPM control register - qcom,isar: Specifies isar bit should be set in the SPM control register Specify this property only if SPM should retain its start address at the end of the program. - qcom,slp_cmd_mode: Specifies slp_cmd_mode bit should be set in SPM control register. Adding this property results in SPM handshaking with RPM. Please remove the RPM handshake command from the sleep sequence, replace that with Sleep without RPM handshake command. - qcom,event_sync: Specifies event_sync byte should be set in SPM control register. ---------------------------------------------------- PSCI targets should follow the rules shown below ---------------------------------------------------- Optional properties for only PSCI targets: - qcom,saw2-avs-ctl: The AVS control register - qcom,saw2-avs-hysterisis: The AVS hysterisis register to delay the AVS controller requests - qcom,vctl-timeout-us: The timeout value in us to wait for voltage to change after sending the voltage command to the PMIC - qcom,saw2-avs-limit: The AVS limit register - qcom,saw2-avs-dly: The AVS delay register is used to specify the delay values between AVS controller requests - qcom,vctl-port: The PVC (PMIC Virtual Channel) port used for changing voltage - qcom,phase-port: The PVC port used for changing the number of phases - qcom,pfm-port: The PVC port used for enabling PWM/PFM modes - qcom,cpu-vctl-list: List of cpu node phandles, whose voltage the spm device can control. Example 1: qcom,spm@f9089000 { compatible = "qcom,spm-v2"; #address-cells = <1>; #size-cells = <1>; reg = <0xf9089000 0x1000>; qcom,cpu = <&CPU0>; qcom,saw2-ver-reg = <0xfd0>; qcom,saw2-cfg = <0x1b>; qcom,saw2-avs-ctl = <0>; qcom,saw2-avs-hysteresis = <0>; qcom,saw2-avs-limit = <0>; qcom,saw2-avs-dly= <0>; qcom,saw2-spm-dly= <0x20000400>; qcom,saw2-spm-ctl = <0x1>; qcom,cpu-vctl-list = <&CPU0 &CPU1 &CPU2 &CPU3>; qcom,mode0 { qcom,label = "qcom,saw2-spm-cmd-wfi"; qcom,sequence = [03 0b 0f]; qcom,spm_en; }; qcom,mode1 { qcom,label = "qcom,saw2-spm-cmd-spc"; qcom,sequence = [00 20 50 80 60 70 10 92 a0 b0 03 68 70 3b 92 a0 b0 82 2b 50 10 30 02 22 30 0f]; qcom,spm_en; qcom,pc_mode; }; qcom,mode2 { qcom,label = "qcom,saw2-spm-cmd-pc"; qcom,sequence = [00 20 10 92 a0 b0 07 3b 92 a0 b0 82 10 30 02 22 30 0f]; qcom,spm_en; qcom,pc_mode; }; }; Example 2: qcom,spm@9A10000 { compatible = "qcom,spm-v2"; #address-cells = <1>; #size-cells = <1>; reg = <0x9A10000 0x1000>; qcom,name = "system-cbf"; /* CBF SAW */ qcom,saw2-ver-reg = <0xFD0>; qcom,cpu-vctl-list = <&CPU0 &CPU1 &CPU2 &CPU3>; qcom,vctl-timeout-us = <50>; qcom,vctl-port = <0x0>; qcom,phase-port = <0x1>; qcom,saw2-avs-ctl = <0x1100>; qcom,pfm-port = <0x2>; }; arch/arm/configs/qcs405-perf_defconfig +2 −0 Original line number Diff line number Diff line Loading @@ -341,6 +341,8 @@ CONFIG_RPMSG_QCOM_SMD=y CONFIG_QCOM_QMI_HELPERS=y CONFIG_QCOM_SMEM=y CONFIG_QCOM_SMD_RPM=y CONFIG_MSM_SPM=y CONFIG_MSM_L2_SPM=y CONFIG_QCOM_SCM=y CONFIG_QCOM_SMP2P=y CONFIG_MSM_SUBSYSTEM_RESTART=y Loading arch/arm/configs/qcs405_defconfig +2 −0 Original line number Diff line number Diff line Loading @@ -361,6 +361,8 @@ CONFIG_RPMSG_QCOM_SMD=y CONFIG_QCOM_QMI_HELPERS=y CONFIG_QCOM_SMEM=y CONFIG_QCOM_SMD_RPM=y CONFIG_MSM_SPM=y CONFIG_MSM_L2_SPM=y CONFIG_QCOM_SCM=y CONFIG_QCOM_SMP2P=y CONFIG_MSM_SUBSYSTEM_RESTART=y Loading arch/arm64/boot/dts/qcom/qcs405-pm.dtsi 0 → 100644 +144 −0 Original line number Diff line number Diff line /* Copyright (c) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and * only version 2 as published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ #include <dt-bindings/msm/pm.h> &soc { qcom,spm@b012000 { compatible = "qcom,spm-v2"; #address-cells = <1>; #size-cells = <1>; reg = <0xb012000 0x1000>; qcom,name = "perf-l2"; qcom,saw2-ver-reg = <0xfd0>; qcom,saw2-cfg = <0x14>; qcom,saw2-spm-dly= <0x3C11840A>; qcom,saw2-spm-ctl = <0xe>; qcom,cpu-vctl-list = <&CPU0 &CPU1 &CPU2 &CPU3>; qcom,vctl-timeout-us = <500>; qcom,vctl-port = <0x0>; }; qcom,lpm-levels { compatible = "qcom,lpm-levels"; qcom,use-psci; #address-cells = <1>; #size-cells = <0>; qcom,pm-cluster@0{ reg = <0>; #address-cells = <1>; #size-cells = <0>; label = "perf"; qcom,psci-mode-shift = <4>; qcom,psci-mode-mask = <0xf>; qcom,pm-cluster-level@0{ reg = <0>; label = "perf-l2-wfi"; qcom,psci-mode = <1>; qcom,latency-us = <180>; qcom,ss-power = <429>; qcom,energy-overhead = <162991>; qcom,time-overhead = <305>; }; qcom,pm-cluster-level@1{ reg = <1>; label = "perf-l2-gdhs"; qcom,psci-mode = <4>; qcom,latency-us = <280>; qcom,ss-power = <421>; qcom,energy-overhead = <257510>; qcom,time-overhead = <520>; qcom,min-child-idx = <1>; qcom,reset-level = <LPM_RESET_LVL_GDHS>; }; qcom,pm-cluster-level@2{ reg = <2>; label = "perf-l2-retention"; qcom,psci-mode = <2>; qcom,latency-us = <650>; qcom,ss-power = <350>; qcom,energy-overhead = <651061>; qcom,time-overhead = <1350>; qcom,min-child-idx = <1>; qcom,reset-level = <LPM_RESET_LVL_RET>; }; qcom,pm-cluster-level@3{ reg = <3>; label = "perf-l2-pc"; qcom,psci-mode = <5>; qcom,latency-us = <11200>; qcom,ss-power = <320>; qcom,energy-overhead = <917561>; qcom,time-overhead = <1700>; qcom,min-child-idx = <1>; qcom,is-reset; qcom,notify-rpm; qcom,reset-level = <LPM_RESET_LVL_PC>; }; qcom,pm-cpu { #address-cells = <1>; #size-cells = <0>; qcom,psci-mode-shift = <0>; qcom,psci-mode-mask = <0xf>; qcom,cpu = <&CPU0 &CPU1 &CPU2 &CPU3>; qcom,pm-cpu-level@0 { reg = <0>; qcom,psci-cpu-mode = <0>; label = "wfi"; qcom,latency-us = <12>; qcom,ss-power = <463>; qcom,energy-overhead = <23520>; qcom,time-overhead = <25>; }; qcom,pm-cpu-level@1 { reg = <1>; qcom,psci-cpu-mode = <3>; label = "pc"; qcom,latency-us = <180>; qcom,ss-power = <429>; qcom,energy-overhead = <162991>; qcom,time-overhead = <305>; qcom,use-broadcast-timer; qcom,is-reset; qcom,reset-level = <LPM_RESET_LVL_PC>; }; }; }; }; qcom,rpm-stats@200000 { compatible = "qcom,rpm-stats"; reg = <0x200000 0x1000>, <0x290014 0x4>, <0x29001c 0x4>; reg-names = "phys_addr_base", "offset_addr", "heap_phys_addrbase"; qcom,sleep-stats-version = <2>; }; qcom,rpm-master-stats@60150 { compatible = "qcom,rpm-master-stats"; reg = <0x60150 0x5000>; qcom,masters = "APSS", "MPSS", "PRONTO", "TZ", "LPASS"; qcom,master-stats-version = <2>; qcom,master-offset = <4096>; }; }; Loading
Documentation/devicetree/bindings/arm/msm/rpm_master_stats.txt 0 → 100644 +47 −0 Original line number Diff line number Diff line * RPM Stats RPM maintains a counter of the masters i.e APPS, MPPS etc number of times the SoC entered a deeper sleep mode involving lowering or powering down the backbone rails - Cx and Mx and the oscillator clock, XO. PROPERTIES - compatible: Usage: required Value type: <string> Definition: Should be "qcom,rpm-master-stats". - reg: Usage: required Value type: <prop-encoded-array> Definition: The address on the RPM RAM from where the stats are read should be provided as "phys_addr_base". The offset from which the stats are available should be provided as "offset_addr". - reg-names: Usage: required Value type: <prop-encoded-array> Definition: Provides labels for the reg property. - qcom,masters: Usage: required Value tye: <string list> Defination: Provides the masters list. qcom,master-offset: Usage: required Value tye: <prop-encoded-array> Defination: Provides the masters list EXAMPLE: qcom,rpm-master-stats@60150 { compatible = "qcom,rpm-master-stats"; reg = <0x60150 0x5000>; qcom,masters = "APSS", "MPSS", "PRONTO", "TZ", "LPASS"; qcom,master-stats-version = <2>; qcom,master-offset = <4096>; };
Documentation/devicetree/bindings/arm/msm/spm-v2.txt 0 → 100644 +169 −0 Original line number Diff line number Diff line * MSM Subsystem Power Manager (spm-v2) S4 generation of MSMs have SPM hardware blocks to control the Application Processor Sub-System power. These SPM blocks run individual state machine to determine what the core (L2 or Krait/Scorpion) would do when the WFI instruction is executed by the core. The SAW hardware block handles SPM and AVS functionality for the cores. The devicetree representation of the SPM block should be: Required properties - compatible: "qcom,spm-v2" - reg: The physical address and the size of the SPM's memory mapped registers - qcom,cpu: phandle for the CPU that the SPM block is attached to. This field is required on only for SPMs that control the CPU. This field is not required for SPMs that control L2/CCI/L3 - qcom,saw2-ver-reg: The location of the version register - qcom,name: The name with which a SPM device is identified by the power management code. ---------------------------------------------------- Non-PSCI targets should follow the rules shown below ---------------------------------------------------- Required properties for only Non-PSCI targets: - qcom,saw2-cfg: SAW2 configuration register - qcom,saw2-spm-ctl: The SPM control register - qcom,saw2-spm-dly: Provides the values for the SPM delay command in the SPM sequence Optional properties for only Non-PSCI targets - reg-names: Register names for the physical address required if spm device has more than one physical addressed to be mapped. Allowed register names are: "saw-base", "q2s", "hw-flush", "slpreq" - qcom,saw2-avs-ctl: The AVS control register - qcom,saw2-avs-hysterisis: The AVS hysterisis register to delay the AVS controller requests - qcom,vctl-timeout-us: The timeout value in us to wait for voltage to change after sending the voltage command to the PMIC - qcom,saw2-avs-limit: The AVS limit register - qcom,saw2-avs-dly: The AVS delay register is used to specify the delay values between AVS controller requests - qcom,saw2-pmic-data0..7: Specify the pmic data value and the associated FTS index to send the PMIC data to - qcom,vctl-port: The PVC (PMIC Virtual Channel) port used for changing voltage - qcom,phase-port: The PVC port used for changing the number of phases - qcom,pfm-port: The PVC port used for enabling PWM/PFM modes - qcom,cpu-vctl-mask: Mask of cpus, whose voltage the spm device can control. Depricated: Replaced with cpu-vctl-list when cpu phandles are available. - qcom,cpu-vctl-list: List of cpu node phandles, whose voltage the spm device can control. - qcom,use-qchannel-for-pc: Boolean property to specify if qchannel should be ignored when entering power collapse. If this property is set qchannel will not be ignored in power collapse. - qcom,supports-rpm-hs: Indicates that this SPM instance allow handshake with RPM processor when executing the sleep command in the SPM sequence. Supported only on SAW2 v3.0 and above. - qcom,use-spm-clock-gating: This boolean property is used to indicate that the SPM needs to be used for clock gating. Using the SPM for clock gating would result in auto clock gating being disabled. Use this on targets that do not support or do not use auto clock gating. - qcom,use-qchannel-for-wfi: This boolean property is used to indicate that the SPM gets triggerd by the qchannel and not by means of wfi. So a wfe could trigger a spm for clock gating as well. - modes: Lists all the available low power modes for the device Second level properties for modes Required properties (if modes node is available) - qcom,label: Specifies the mode name such as: qcom,saw2-spm-cmd-wfi: WFI mode qcom,saw2-spm-cmd-ret: Retention mode qcom,saw2-spm-cmd-spc: Standalone PC mode qcom,saw2-spm-cmd-pc: Power Collapse mode qcom,saw2-spm-cmd-gdhs: GDHS mode - qcom,sequence: Specifies sequence for the low power mode Optional properties - qcom,pc_mode: Specifies pc_mode bit should be set in the SPM control register - qcom,ret_mode: Specifies ret_mode bit should be set in the SPM control register - qcom,spm_en: Specifies spm_en bit should be set in the SPM control register - qcom,isar: Specifies isar bit should be set in the SPM control register Specify this property only if SPM should retain its start address at the end of the program. - qcom,slp_cmd_mode: Specifies slp_cmd_mode bit should be set in SPM control register. Adding this property results in SPM handshaking with RPM. Please remove the RPM handshake command from the sleep sequence, replace that with Sleep without RPM handshake command. - qcom,event_sync: Specifies event_sync byte should be set in SPM control register. ---------------------------------------------------- PSCI targets should follow the rules shown below ---------------------------------------------------- Optional properties for only PSCI targets: - qcom,saw2-avs-ctl: The AVS control register - qcom,saw2-avs-hysterisis: The AVS hysterisis register to delay the AVS controller requests - qcom,vctl-timeout-us: The timeout value in us to wait for voltage to change after sending the voltage command to the PMIC - qcom,saw2-avs-limit: The AVS limit register - qcom,saw2-avs-dly: The AVS delay register is used to specify the delay values between AVS controller requests - qcom,vctl-port: The PVC (PMIC Virtual Channel) port used for changing voltage - qcom,phase-port: The PVC port used for changing the number of phases - qcom,pfm-port: The PVC port used for enabling PWM/PFM modes - qcom,cpu-vctl-list: List of cpu node phandles, whose voltage the spm device can control. Example 1: qcom,spm@f9089000 { compatible = "qcom,spm-v2"; #address-cells = <1>; #size-cells = <1>; reg = <0xf9089000 0x1000>; qcom,cpu = <&CPU0>; qcom,saw2-ver-reg = <0xfd0>; qcom,saw2-cfg = <0x1b>; qcom,saw2-avs-ctl = <0>; qcom,saw2-avs-hysteresis = <0>; qcom,saw2-avs-limit = <0>; qcom,saw2-avs-dly= <0>; qcom,saw2-spm-dly= <0x20000400>; qcom,saw2-spm-ctl = <0x1>; qcom,cpu-vctl-list = <&CPU0 &CPU1 &CPU2 &CPU3>; qcom,mode0 { qcom,label = "qcom,saw2-spm-cmd-wfi"; qcom,sequence = [03 0b 0f]; qcom,spm_en; }; qcom,mode1 { qcom,label = "qcom,saw2-spm-cmd-spc"; qcom,sequence = [00 20 50 80 60 70 10 92 a0 b0 03 68 70 3b 92 a0 b0 82 2b 50 10 30 02 22 30 0f]; qcom,spm_en; qcom,pc_mode; }; qcom,mode2 { qcom,label = "qcom,saw2-spm-cmd-pc"; qcom,sequence = [00 20 10 92 a0 b0 07 3b 92 a0 b0 82 10 30 02 22 30 0f]; qcom,spm_en; qcom,pc_mode; }; }; Example 2: qcom,spm@9A10000 { compatible = "qcom,spm-v2"; #address-cells = <1>; #size-cells = <1>; reg = <0x9A10000 0x1000>; qcom,name = "system-cbf"; /* CBF SAW */ qcom,saw2-ver-reg = <0xFD0>; qcom,cpu-vctl-list = <&CPU0 &CPU1 &CPU2 &CPU3>; qcom,vctl-timeout-us = <50>; qcom,vctl-port = <0x0>; qcom,phase-port = <0x1>; qcom,saw2-avs-ctl = <0x1100>; qcom,pfm-port = <0x2>; };
arch/arm/configs/qcs405-perf_defconfig +2 −0 Original line number Diff line number Diff line Loading @@ -341,6 +341,8 @@ CONFIG_RPMSG_QCOM_SMD=y CONFIG_QCOM_QMI_HELPERS=y CONFIG_QCOM_SMEM=y CONFIG_QCOM_SMD_RPM=y CONFIG_MSM_SPM=y CONFIG_MSM_L2_SPM=y CONFIG_QCOM_SCM=y CONFIG_QCOM_SMP2P=y CONFIG_MSM_SUBSYSTEM_RESTART=y Loading
arch/arm/configs/qcs405_defconfig +2 −0 Original line number Diff line number Diff line Loading @@ -361,6 +361,8 @@ CONFIG_RPMSG_QCOM_SMD=y CONFIG_QCOM_QMI_HELPERS=y CONFIG_QCOM_SMEM=y CONFIG_QCOM_SMD_RPM=y CONFIG_MSM_SPM=y CONFIG_MSM_L2_SPM=y CONFIG_QCOM_SCM=y CONFIG_QCOM_SMP2P=y CONFIG_MSM_SUBSYSTEM_RESTART=y Loading
arch/arm64/boot/dts/qcom/qcs405-pm.dtsi 0 → 100644 +144 −0 Original line number Diff line number Diff line /* Copyright (c) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and * only version 2 as published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ #include <dt-bindings/msm/pm.h> &soc { qcom,spm@b012000 { compatible = "qcom,spm-v2"; #address-cells = <1>; #size-cells = <1>; reg = <0xb012000 0x1000>; qcom,name = "perf-l2"; qcom,saw2-ver-reg = <0xfd0>; qcom,saw2-cfg = <0x14>; qcom,saw2-spm-dly= <0x3C11840A>; qcom,saw2-spm-ctl = <0xe>; qcom,cpu-vctl-list = <&CPU0 &CPU1 &CPU2 &CPU3>; qcom,vctl-timeout-us = <500>; qcom,vctl-port = <0x0>; }; qcom,lpm-levels { compatible = "qcom,lpm-levels"; qcom,use-psci; #address-cells = <1>; #size-cells = <0>; qcom,pm-cluster@0{ reg = <0>; #address-cells = <1>; #size-cells = <0>; label = "perf"; qcom,psci-mode-shift = <4>; qcom,psci-mode-mask = <0xf>; qcom,pm-cluster-level@0{ reg = <0>; label = "perf-l2-wfi"; qcom,psci-mode = <1>; qcom,latency-us = <180>; qcom,ss-power = <429>; qcom,energy-overhead = <162991>; qcom,time-overhead = <305>; }; qcom,pm-cluster-level@1{ reg = <1>; label = "perf-l2-gdhs"; qcom,psci-mode = <4>; qcom,latency-us = <280>; qcom,ss-power = <421>; qcom,energy-overhead = <257510>; qcom,time-overhead = <520>; qcom,min-child-idx = <1>; qcom,reset-level = <LPM_RESET_LVL_GDHS>; }; qcom,pm-cluster-level@2{ reg = <2>; label = "perf-l2-retention"; qcom,psci-mode = <2>; qcom,latency-us = <650>; qcom,ss-power = <350>; qcom,energy-overhead = <651061>; qcom,time-overhead = <1350>; qcom,min-child-idx = <1>; qcom,reset-level = <LPM_RESET_LVL_RET>; }; qcom,pm-cluster-level@3{ reg = <3>; label = "perf-l2-pc"; qcom,psci-mode = <5>; qcom,latency-us = <11200>; qcom,ss-power = <320>; qcom,energy-overhead = <917561>; qcom,time-overhead = <1700>; qcom,min-child-idx = <1>; qcom,is-reset; qcom,notify-rpm; qcom,reset-level = <LPM_RESET_LVL_PC>; }; qcom,pm-cpu { #address-cells = <1>; #size-cells = <0>; qcom,psci-mode-shift = <0>; qcom,psci-mode-mask = <0xf>; qcom,cpu = <&CPU0 &CPU1 &CPU2 &CPU3>; qcom,pm-cpu-level@0 { reg = <0>; qcom,psci-cpu-mode = <0>; label = "wfi"; qcom,latency-us = <12>; qcom,ss-power = <463>; qcom,energy-overhead = <23520>; qcom,time-overhead = <25>; }; qcom,pm-cpu-level@1 { reg = <1>; qcom,psci-cpu-mode = <3>; label = "pc"; qcom,latency-us = <180>; qcom,ss-power = <429>; qcom,energy-overhead = <162991>; qcom,time-overhead = <305>; qcom,use-broadcast-timer; qcom,is-reset; qcom,reset-level = <LPM_RESET_LVL_PC>; }; }; }; }; qcom,rpm-stats@200000 { compatible = "qcom,rpm-stats"; reg = <0x200000 0x1000>, <0x290014 0x4>, <0x29001c 0x4>; reg-names = "phys_addr_base", "offset_addr", "heap_phys_addrbase"; qcom,sleep-stats-version = <2>; }; qcom,rpm-master-stats@60150 { compatible = "qcom,rpm-master-stats"; reg = <0x60150 0x5000>; qcom,masters = "APSS", "MPSS", "PRONTO", "TZ", "LPASS"; qcom,master-stats-version = <2>; qcom,master-offset = <4096>; }; };
