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Commit 5a35e99e authored by Damien Lespiau's avatar Damien Lespiau Committed by Daniel Vetter
Browse files

drm/i915: adjust sprite base address 



Just like in:

commit c2c75131
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date:   Thu Jul 5 12:17:30 2012 +0200

    drm/i915: adjust framebuffer base address on gen4+

but this time, for the sprite planes. This ensures that the
sprite offset are always inside the supported hardware limits since it
becomes the offset into a page and we adjust the base address to a page
boundary.

Signed-off-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent c54173a8

drivers/gpu/drm/i915/intel_display.c

+9 −9
Original line number Diff line number Diff line
@@ -1955,7 +1955,7 @@ void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) 


/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel

 * is assumed to be a power-of-two. */

static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y,

unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,

					       unsigned int bpp,

					       unsigned int pitch)

{
@@ -2029,7 +2029,7 @@ static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, 


	if (INTEL_INFO(dev)->gen >= 4) {

		intel_crtc->dspaddr_offset =

			gen4_compute_dspaddr_offset_xtiled(&x, &y,

			intel_gen4_compute_offset_xtiled(&x, &y,

							 fb->bits_per_pixel / 8,

							 fb->pitches[0]);

		linear_offset -= intel_crtc->dspaddr_offset;
@@ -2118,7 +2118,7 @@ static int ironlake_update_plane(struct drm_crtc *crtc, 


	linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);

	intel_crtc->dspaddr_offset =

		gen4_compute_dspaddr_offset_xtiled(&x, &y,

		intel_gen4_compute_offset_xtiled(&x, &y,

						 fb->bits_per_pixel / 8,

						 fb->pitches[0]);

	linear_offset -= intel_crtc->dspaddr_offset;

drivers/gpu/drm/i915/intel_drv.h

+4 −0
Original line number Diff line number Diff line
@@ -585,6 +585,10 @@ extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe, 
extern void intel_update_linetime_watermarks(struct drm_device *dev, int pipe,

			 struct drm_display_mode *mode);



extern unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,

						      unsigned int bpp,

						      unsigned int pitch);



extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data,

				     struct drm_file *file_priv);

extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data,

drivers/gpu/drm/i915/intel_sprite.c

+28 −18
Original line number Diff line number Diff line
@@ -49,6 +49,7 @@ ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb, 
	int pipe = intel_plane->pipe;

	u32 sprctl, sprscale = 0;

	int pixel_size;

	unsigned long sprsurf_offset, linear_offset;



	sprctl = I915_READ(SPRCTL(pipe));
@@ -128,24 +129,27 @@ ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb, 
	I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);

	I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);



	if (IS_HASWELL(dev)) {

		/* HSW consolidates SPRTILEOFF and SPRLINOFF into a single

		 * SPROFFSET register */

	linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);

	sprsurf_offset =

		intel_gen4_compute_offset_xtiled(&x, &y,

						 fb->bits_per_pixel / 8,

						 fb->pitches[0]);

	linear_offset -= sprsurf_offset;



	/* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET

	 * register */

	if (IS_HASWELL(dev))

		I915_WRITE(SPROFFSET(pipe), (y << 16) | x);

	} else if (obj->tiling_mode != I915_TILING_NONE) {

	else if (obj->tiling_mode != I915_TILING_NONE)

		I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);

	} else {

		unsigned long offset;



		offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);

		I915_WRITE(SPRLINOFF(pipe), offset);

	}

	else

		I915_WRITE(SPRLINOFF(pipe), linear_offset);



	I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);

	if (intel_plane->can_scale)

		I915_WRITE(SPRSCALE(pipe), sprscale);

	I915_WRITE(SPRCTL(pipe), sprctl);

	I915_MODIFY_DISPBASE(SPRSURF(pipe), obj->gtt_offset);

	I915_MODIFY_DISPBASE(SPRSURF(pipe), obj->gtt_offset + sprsurf_offset);

	POSTING_READ(SPRSURF(pipe));

}
@@ -234,6 +238,7 @@ ilk_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb, 
	struct drm_i915_private *dev_priv = dev->dev_private;

	struct intel_plane *intel_plane = to_intel_plane(plane);

	int pipe = intel_plane->pipe, pixel_size;

	unsigned long dvssurf_offset, linear_offset;

	u32 dvscntr, dvsscale;



	dvscntr = I915_READ(DVSCNTR(pipe));
@@ -297,18 +302,23 @@ ilk_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb, 


	I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);

	I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);

	if (obj->tiling_mode != I915_TILING_NONE) {



	linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);

	dvssurf_offset =

		intel_gen4_compute_offset_xtiled(&x, &y,

						 fb->bits_per_pixel / 8,

						 fb->pitches[0]);

	linear_offset -= dvssurf_offset;



	if (obj->tiling_mode != I915_TILING_NONE)

		I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x);

	} else {

		unsigned long offset;

	else

		I915_WRITE(DVSLINOFF(pipe), linear_offset);



		offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);

		I915_WRITE(DVSLINOFF(pipe), offset);

	}

	I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);

	I915_WRITE(DVSSCALE(pipe), dvsscale);

	I915_WRITE(DVSCNTR(pipe), dvscntr);

	I915_MODIFY_DISPBASE(DVSSURF(pipe), obj->gtt_offset);

	I915_MODIFY_DISPBASE(DVSSURF(pipe), obj->gtt_offset + dvssurf_offset);

	POSTING_READ(DVSSURF(pipe));

}