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Commit 598056d5 authored by Nick Piggin's avatar Nick Piggin Committed by Paul Mackerras
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[POWERPC] Fix rmb to order cacheable vs. noncacheable 



lwsync is explicitly defined not to have any effect on the ordering of
accesses to device memory, so it cannot be used for rmb(). sync appears
to be the only barrier which fits the bill.

Signed-off-by: default avatarNick Piggin <npiggin@suse.de>
Acked-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
parent a9653cf5

include/asm-powerpc/system.h

+1 −1
Original line number Diff line number Diff line
@@ -34,7 +34,7 @@ 
 * SMP since it is only used to order updates to system memory.

 */

#define mb()   __asm__ __volatile__ ("sync" : : : "memory")

#define rmb()  __asm__ __volatile__ (__stringify(LWSYNC) : : : "memory")

#define rmb()  __asm__ __volatile__ ("sync" : : : "memory")

#define wmb()  __asm__ __volatile__ ("sync" : : : "memory")

#define read_barrier_depends()  do { } while(0)