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Commit 58fb7b9c authored by Santosh Mardi's avatar Santosh Mardi
Browse files

ARM: dts: msm: add support for the stall based memlat 



Add support for the stall based memlat for memlat nodes
on sm6150 target

Change-Id: I746cd36e41a63131cbce6917d11b9314da781c5b
Signed-off-by: default avatarSantosh Mardi <gsantosh@codeaurora.org>
parent 99d2a792

arch/arm64/boot/dts/qcom/sm6150.dtsi

+6 −0
Original line number Diff line number Diff line
@@ -2501,6 +2501,7 @@ 
		qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;

		qcom,target-dev = <&cpu0_cpu_l3_lat>;

		qcom,cachemiss-ev = <0x17>;

		qcom,stall-cycle-ev = <0xE7>;

		qcom,core-dev-table =

			<  576000  300000000 >,

			< 1017600  556800000 >,
@@ -2521,6 +2522,7 @@ 
		qcom,cpulist = <&CPU6 &CPU7>;

		qcom,target-dev = <&cpu6_cpu_l3_lat>;

		qcom,cachemiss-ev = <0x17>;

		qcom,stall-cycle-ev = <0x15E>;

		qcom,core-dev-table =

			< 1017600  556800000 >,

			< 1209600  806400000 >,
@@ -2543,6 +2545,7 @@ 
		qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;

		qcom,target-dev = <&cpu0_cpu_llcc_lat>;

		qcom,cachemiss-ev = <0x2A>;

		qcom,stall-cycle-ev = <0xE7>;

		qcom,core-dev-table =

			<  748000 MHZ_TO_MBPS(150, 16) >,

			< 1209600 MHZ_TO_MBPS(300, 16) >,
@@ -2564,6 +2567,7 @@ 
		qcom,cpulist = <&CPU6 &CPU7>;

		qcom,target-dev = <&cpu6_cpu_llcc_lat>;

		qcom,cachemiss-ev = <0x2A>;

		qcom,stall-cycle-ev = <0x15E>;

		qcom,core-dev-table =

			<  768000 MHZ_TO_MBPS(300, 16) >,

			< 1017600 MHZ_TO_MBPS(466, 16) >,
@@ -2586,6 +2590,7 @@ 
		qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;

		qcom,target-dev = <&cpu0_llcc_ddr_lat>;

		qcom,cachemiss-ev = <0x1000>;

		qcom,stall-cycle-ev = <0xE7>;

		qcom,core-dev-table =

			<  748000 MHZ_TO_MBPS( 300, 4) >,

			< 1017600 MHZ_TO_MBPS( 451, 4) >,
@@ -2608,6 +2613,7 @@ 
		qcom,cpulist = <&CPU6 &CPU7>;

		qcom,target-dev = <&cpu6_llcc_ddr_lat>;

		qcom,cachemiss-ev = <0x1000>;

		qcom,stall-cycle-ev = <0x15E>;

		qcom,core-dev-table =

			<  768000 MHZ_TO_MBPS( 451, 4) >,

			< 1017600 MHZ_TO_MBPS( 547, 4) >,