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Commit 58ea94ae authored by Karthik Anantha Ram's avatar Karthik Anantha Ram Committed by Gerrit - the friendly Code Review server
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msm: camera: isp: Reduce logging as part of camif dump 



Currently when an error irq is encountered; the entire vfe
register space is dumped which can cause a WD bite.
This change dumps only necessary registers which would help
infer the cause for the error.

Change-Id: If67a71877ea85175d09b9226db1b8e38c7c3b3f0
Signed-off-by: default avatarKarthik Anantha Ram <kartanan@codeaurora.org>
parent 5c24593c

drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver2.c

+66 −64
Original line number Diff line number Diff line
@@ -314,12 +314,55 @@ static int cam_vfe_camif_resource_start( 
}



static int cam_vfe_camif_reg_dump(

	struct cam_vfe_mux_camif_data *camif_priv)

{

	uint32_t val = 0, wm_idx, offset;

	int i = 0;



	for (i = 0xA3C; i <= 0xA90; i += 8) {

		CAM_INFO(CAM_ISP,

			"SCALING offset 0x%x val 0x%x offset 0x%x val 0x%x",

			i, cam_io_r_mb(camif_priv->mem_base + i), i + 4,

			cam_io_r_mb(camif_priv->mem_base + i + 4));

	}



	for (i = 0xE0C; i <= 0xE3C; i += 4) {

		val = cam_io_r_mb(camif_priv->mem_base + i);

		CAM_INFO(CAM_ISP, "offset 0x%x val 0x%x", i, val);

	}



	for (wm_idx = 0; wm_idx <= 23; wm_idx++) {

		offset = 0x2214 + 0x100 * wm_idx;

		CAM_INFO(CAM_ISP,

			"BUS_WM%u offset 0x%x val 0x%x offset 0x%x val 0x%x",

			wm_idx, offset,

			cam_io_r_mb(camif_priv->mem_base + offset),

			offset + 4, cam_io_r_mb(camif_priv->mem_base +

			offset + 4), offset + 8,

			cam_io_r_mb(camif_priv->mem_base + offset + 8),

			offset + 12, cam_io_r_mb(camif_priv->mem_base +

			offset + 12));

	}



	offset = 0x420;

	val = cam_soc_util_r(camif_priv->soc_info, 1, offset);

	CAM_INFO(CAM_ISP, "CAMNOC IFE02 MaxWR_LOW offset 0x%x value 0x%x",

		offset, val);



	offset = 0x820;

	val = cam_soc_util_r(camif_priv->soc_info, 1, offset);

	CAM_INFO(CAM_ISP, "CAMNOC IFE13 MaxWR_LOW offset 0x%x value 0x%x",

		offset, val);



	return 0;

}



static int cam_vfe_camif_reg_dump_bh(

	struct cam_isp_resource_node *camif_res)

{

	struct cam_vfe_mux_camif_data *camif_priv;

	struct cam_vfe_soc_private *soc_private;

	int rc = 0, i;

	uint32_t val = 0;

	uint32_t offset, val, wm_idx;



	if (!camif_res) {

		CAM_ERR(CAM_ISP, "Error! Invalid input arguments");
@@ -331,91 +374,50 @@ static int cam_vfe_camif_reg_dump( 
		return 0;



	camif_priv = (struct cam_vfe_mux_camif_data *)camif_res->res_priv;

	soc_private = camif_priv->soc_info->soc_private;

	for (i = 0xA3C; i <= 0xA90; i += 4) {

		val = cam_io_r_mb(camif_priv->mem_base + i);

		CAM_INFO(CAM_ISP, "offset 0x%x val 0x%x", i, val);

	}



	for (i = 0xE0C; i <= 0xE3C; i += 4) {

		val = cam_io_r_mb(camif_priv->mem_base + i);

		CAM_INFO(CAM_ISP, "offset 0x%x val 0x%x", i, val);

	for (offset = 0x0; offset < 0x1000; offset += 0x4) {

		val = cam_soc_util_r(camif_priv->soc_info, 0, offset);

		CAM_DBG(CAM_ISP, "offset 0x%x value 0x%x", offset, val);

	}



	for (i = 0x2000; i <= 0x20B8; i += 4) {

		val = cam_io_r_mb(camif_priv->mem_base + i);

		CAM_INFO(CAM_ISP, "offset 0x%x val 0x%x", i, val);

	for (offset = 0x2000; offset <= 0x20B8; offset += 0x4) {

		val = cam_soc_util_r(camif_priv->soc_info, 0, offset);

		CAM_DBG(CAM_ISP, "offset 0x%x value 0x%x", offset, val);

	}



	for (i = 0x2500; i <= 0x255C; i += 4) {

		val = cam_io_r_mb(camif_priv->mem_base + i);

		CAM_INFO(CAM_ISP, "offset 0x%x val 0x%x", i, val);

	for (wm_idx = 0; wm_idx <= 23; wm_idx++) {

		for (offset = 0x2200 + 0x100 * wm_idx;

			offset < 0x2278 + 0x100 * wm_idx; offset += 0x4) {

			val = cam_soc_util_r(camif_priv->soc_info, 0, offset);

			CAM_DBG(CAM_ISP,

				"offset 0x%x value 0x%x", offset, val);

		}



	for (i = 0x2600; i <= 0x265C; i += 4) {

		val = cam_io_r_mb(camif_priv->mem_base + i);

		CAM_INFO(CAM_ISP, "offset 0x%x val 0x%x", i, val);

	}



	soc_private = camif_priv->soc_info->soc_private;

	if (soc_private->cpas_version == CAM_CPAS_TITAN_175_V120) {

		cam_cpas_reg_read(soc_private->cpas_handle[0],

			CAM_CPAS_REG_CAMNOC, 0x3A20, true, &val);

		CAM_INFO(CAM_ISP, "IFE0_nRDI_MAXWR_LOW offset 0x3A20 val 0x%x",

		CAM_DBG(CAM_ISP, "IFE0_nRDI_MAXWR_LOW offset 0x3A20 val 0x%x",

			val);



		cam_cpas_reg_read(soc_private->cpas_handle[0],

			CAM_CPAS_REG_CAMNOC, 0x5420, true, &val);

		CAM_INFO(CAM_ISP, "IFE1_nRDI_MAXWR_LOW offset 0x5420 val 0x%x",

		CAM_DBG(CAM_ISP, "IFE1_nRDI_MAXWR_LOW offset 0x5420 val 0x%x",

			val);



		cam_cpas_reg_read(soc_private->cpas_handle[1],

			CAM_CPAS_REG_CAMNOC, 0x3620, true, &val);

		CAM_INFO(CAM_ISP,

		CAM_DBG(CAM_ISP,

			"IFE0123_RDI_WR_MAXWR_LOW offset 0x3620 val 0x%x", val);

	} else {

		cam_cpas_reg_read(soc_private->cpas_handle[0],

			CAM_CPAS_REG_CAMNOC, 0x420, true, &val);

		CAM_INFO(CAM_ISP, "IFE02_MAXWR_LOW offset 0x420 val 0x%x", val);

		CAM_DBG(CAM_ISP, "IFE02_MAXWR_LOW offset 0x420 val 0x%x", val);



		cam_cpas_reg_read(soc_private->cpas_handle[0],

			CAM_CPAS_REG_CAMNOC, 0x820, true, &val);

		CAM_INFO(CAM_ISP, "IFE13_MAXWR_LOW offset 0x820 val 0x%x", val);

		CAM_DBG(CAM_ISP, "IFE13_MAXWR_LOW offset 0x820 val 0x%x", val);

	}

	return rc;

}



static int cam_vfe_camif_reg_dump_bh(struct cam_vfe_mux_camif_data *camif_priv)

{

	uint32_t offset, val, wm_idx;



	for (offset = 0x0; offset < 0x1000; offset += 0x4) {

		val = cam_soc_util_r(camif_priv->soc_info, 0, offset);

		CAM_INFO(CAM_ISP, "offset 0x%x value 0x%x", offset, val);

	}



	for (offset = 0x2000; offset <= 0x20B8; offset += 0x4) {

		val = cam_soc_util_r(camif_priv->soc_info, 0, offset);

		CAM_INFO(CAM_ISP, "offset 0x%x value 0x%x", offset, val);

	}



	for (wm_idx = 0; wm_idx <= 23; wm_idx++) {

		for (offset = 0x2200 + 0x100 * wm_idx;

			offset < 0x2278 + 0x100 * wm_idx; offset += 0x4) {

			val = cam_soc_util_r(camif_priv->soc_info, 0, offset);

			CAM_INFO(CAM_ISP,

				"offset 0x%x value 0x%x", offset, val);

		}

	}



	offset = 0x420;

	val = cam_soc_util_r(camif_priv->soc_info, 1, offset);

	CAM_INFO(CAM_ISP, "CAMNOC IFE02 MaxWR_LOW offset 0x%x value 0x%x",

		offset, val);



	offset = 0x820;

	val = cam_soc_util_r(camif_priv->soc_info, 1, offset);

	CAM_INFO(CAM_ISP, "CAMNOC IFE13 MaxWR_LOW offset 0x%x value 0x%x",

		offset, val);



	return 0;

}
@@ -497,7 +499,7 @@ static int cam_vfe_camif_process_cmd(struct cam_isp_resource_node *rsrc_node, 
			arg_size);

		break;

	case CAM_ISP_HW_CMD_GET_REG_DUMP:

		rc = cam_vfe_camif_reg_dump(rsrc_node);

		rc = cam_vfe_camif_reg_dump_bh(rsrc_node);

		break;

	case CAM_ISP_HW_CMD_SOF_IRQ_DEBUG:

		rc = cam_vfe_camif_sof_irq_debug(rsrc_node, cmd_args);
@@ -590,7 +592,7 @@ static int cam_vfe_camif_handle_irq_bottom_half(void *handler_priv, 
		if (irq_status1 & camif_priv->reg_data->error_irq_mask1) {

			CAM_DBG(CAM_ISP, "Received ERROR\n");

			ret = CAM_ISP_HW_ERROR_OVERFLOW;

			cam_vfe_camif_reg_dump_bh(camif_node->res_priv);

			cam_vfe_camif_reg_dump(camif_node->res_priv);

		} else {

			ret = CAM_ISP_HW_ERROR_NONE;

		}