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Commit 58d0c330 authored by Suresh Vankadara's avatar Suresh Vankadara Committed by Gerrit - the friendly Code Review server
Browse files

Merge "msm: camera: sensor: Add csi phy reset sequence" into dev/msm-4.14-camx

parents 94998929 7184e724

drivers/media/platform/msm/camera/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_hwreg.h

+3 −2
Original line number Diff line number Diff line 
/* Copyright (c) 2018, The Linux Foundation. All rights reserved.

/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -20,7 +20,7 @@ struct csiphy_reg_parms_t csiphy_v1_2 = { 
	.mipi_csiphy_interrupt_clear0_addr = 0x858,

	.mipi_csiphy_glbl_irq_cmd_addr = 0x828,

	.csiphy_common_array_size = 4,

	.csiphy_reset_array_size = 4,

	.csiphy_reset_array_size = 5,

	.csiphy_2ph_config_array_size = 21,

	.csiphy_3ph_config_array_size = 31,

	.csiphy_2ph_clock_lane = 0x1,
@@ -38,6 +38,7 @@ struct csiphy_reg_t csiphy_reset_reg_1_2[] = { 
	{0x0814, 0x00, 0x05, CSIPHY_LANE_ENABLE},

	{0x0818, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},

	{0x081C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},

	{0x0800, 0x01, 0x01, CSIPHY_DEFAULT_PARAMS},

	{0x0800, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},

};

drivers/media/platform/msm/camera/cam_sensor_module/cam_csiphy/include/cam_csiphy_2_0_hwreg.h

+7 −3
Original line number Diff line number Diff line 
/* Copyright (c) 2018, The Linux Foundation. All rights reserved.

/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -19,8 +19,8 @@ struct csiphy_reg_parms_t csiphy_v2_0 = { 
	.mipi_csiphy_interrupt_status0_addr = 0x8B0,

	.mipi_csiphy_interrupt_clear0_addr = 0x858,

	.mipi_csiphy_glbl_irq_cmd_addr = 0x828,

	.csiphy_common_array_size = 6,

	.csiphy_reset_array_size = 3,

	.csiphy_common_array_size = 8,

	.csiphy_reset_array_size = 5,

	.csiphy_2ph_config_array_size = 15,

	.csiphy_3ph_config_array_size = 17,

	.csiphy_2ph_clock_lane = 0x1,
@@ -31,6 +31,8 @@ struct csiphy_reg_t csiphy_common_reg_2_0[] = { 
	{0x0814, 0x00, 0x00, CSIPHY_LANE_ENABLE},

	{0x0818, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},

	{0x081C, 0x06, 0x00, CSIPHY_3PH_REGS},

	{0x0800, 0x01, 0x01, CSIPHY_DEFAULT_PARAMS},

	{0x0800, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},

	{0x0164, 0x00, 0x00, CSIPHY_2PH_REGS},

	{0x0364, 0x00, 0x00, CSIPHY_2PH_REGS},

	{0x0564, 0x00, 0x00, CSIPHY_2PH_REGS},
@@ -40,6 +42,8 @@ struct csiphy_reg_t csiphy_reset_reg_2_0[] = { 
	{0x0814, 0x00, 0x05, CSIPHY_LANE_ENABLE},

	{0x0818, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},

	{0x081C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},

	{0x0800, 0x01, 0x01, CSIPHY_DEFAULT_PARAMS},

	{0x0800, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},

};



struct csiphy_reg_t csiphy_irq_reg_2_0[] = {