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Commit 587ae4ba authored by Sandeep Panda's avatar Sandeep Panda Committed by Gerrit - the friendly Code Review server
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drm/msm/dsi-staging: add support for custom cmd dma scheduling 



Some panels take more time to post-process the video data sent
from dsi host and hence BTA acknowledgment may take more than
one line time. This will cause dsi host to miss out sync packets
and which in turn will manifest as corruption on display panel.
To fix this, dsi host should send the BTA request after some
specified lines, once vertical active area ends. This change
adds support for configuring the custom line number at which
command dma needs to be scheduled to avoid such issues.

Change-Id: I3c83310dd755881c78fed9486f81f71d1e29916e
Signed-off-by: default avatarSandeep Panda <spanda@codeaurora.org>
parent 38454009

Documentation/devicetree/bindings/drm/msm/mdss-dsi-panel.txt

+3 −0
Original line number Diff line number Diff line
@@ -529,6 +529,8 @@ Optional properties: 
					display. The first set is indexed by the

					value 0.

- qcom,mdss-dsi-ext-bridge-mode:	External bridge chip is connected instead of panel.

- qcom,mdss-dsi-dma-schedule-line:	An integer value indicates the line number after vertical active

					region, at which command DMA needs to be triggered.



Required properties for sub-nodes:	None

Optional properties:
@@ -786,5 +788,6 @@ Example: 
		qcom,display-topology = <1 1 1>,

			                <2 2 1>;

		qcom,default-topology-index = <0>;

		qcom,mdss-dsi-dma-schedule-line = <5>;

	};

};

drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c

+5 −0
Original line number Diff line number Diff line
@@ -1194,6 +1194,11 @@ static int dsi_message_tx(struct dsi_ctrl *dsi_ctrl, 
	}



kickoff:

	/* check if custom dma scheduling line needed */

	if ((dsi_ctrl->host_config.panel_mode == DSI_OP_VIDEO_MODE) &&

		(flags & DSI_CTRL_CMD_CUSTOM_DMA_SCHED))

		line_no = dsi_ctrl->host_config.u.video_engine.dma_sched_line;



	timing = &(dsi_ctrl->host_config.video_timing);

	if (timing)

		line_no += timing->v_back_porch + timing->v_sync_width +

drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.h

+3 −0
Original line number Diff line number Diff line
@@ -38,6 +38,8 @@ 
 * @DSI_CTRL_CMD_LAST_COMMAND:     Trigger the DMA cmd transfer if this is last

 *				   command in the batch.

 * @DSI_CTRL_CMD_NON_EMBEDDED_MODE:Transfer cmd packets in non embedded mode.

 * @DSI_CTRL_CMD_CUSTOM_DMA_SCHED: Use the dma scheduling line number defined in

 *				   display panel dtsi file instead of default.

 */

#define DSI_CTRL_CMD_READ             0x1

#define DSI_CTRL_CMD_BROADCAST        0x2
@@ -47,6 +49,7 @@ 
#define DSI_CTRL_CMD_FETCH_MEMORY     0x20

#define DSI_CTRL_CMD_LAST_COMMAND     0x40

#define DSI_CTRL_CMD_NON_EMBEDDED_MODE 0x80

#define DSI_CTRL_CMD_CUSTOM_DMA_SCHED  0x100



/* DSI embedded mode fifo size

 * If the command is greater than 256 bytes it is sent in non-embedded mode.

drivers/gpu/drm/msm/dsi-staging/dsi_defs.h

+3 −0
Original line number Diff line number Diff line
@@ -458,6 +458,8 @@ struct dsi_host_common_cfg { 
 * @bllp_lp11_en:              Enter low power stop mode (LP-11) during BLLP.

 * @traffic_mode:              Traffic mode for video stream.

 * @vc_id:                     Virtual channel identifier.

 * @dma_sched_line:         Line number, after vactive end, at which command dma

 *			       needs to be triggered.

 */

struct dsi_video_engine_cfg {

	bool last_line_interleave_en;
@@ -470,6 +472,7 @@ struct dsi_video_engine_cfg { 
	bool force_clk_lane_hs;

	enum dsi_video_traffic_mode traffic_mode;

	u32 vc_id;

	u32 dma_sched_line;

};



/**

drivers/gpu/drm/msm/dsi-staging/dsi_display.c

+2 −1
Original line number Diff line number Diff line
@@ -643,7 +643,8 @@ static int dsi_display_read_status(struct dsi_display_ctrl *ctrl, 
	lenp = config->status_valid_params ?: config->status_cmds_rlen;

	count = config->status_cmd.count;

	cmds = config->status_cmd.cmds;

	flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ);

	flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ |

		  DSI_CTRL_CMD_CUSTOM_DMA_SCHED);



	for (i = 0; i < count; ++i) {

		memset(config->status_buf, 0x0, SZ_4K);