Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 581fb90a authored by Taniya Das's avatar Taniya Das Committed by Gerrit - the friendly Code Review server
Browse files

clk: qcom: Add active only xo parent source for XO clocks 



The XO clock sources from camcc/videocc/dispcc requires to vote for active
only clock source, so as to not block XO. While at it also remove VDD
voting for xo clock source.

Change-Id: I6966da45f794acc82e7163f7ffabf3f67c666940
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent 7ad3d3b9

drivers/clk/qcom/camcc-sdmmagpie.c

+1 −1
Original line number Diff line number Diff line
@@ -188,7 +188,7 @@ static const struct parent_map cam_cc_parent_map_9[] = { 
};



static const char * const cam_cc_parent_names_9[] = {

	"bi_tcxo",

	"bi_tcxo_ao",

	"core_bi_pll_test_se",

};

drivers/clk/qcom/dispcc-sdmmagpie.c

+6 −5
Original line number Diff line number Diff line
@@ -93,6 +93,11 @@ static const char * const disp_cc_parent_names_2[] = { 
	"core_bi_pll_test_se",

};



static const char * const disp_cc_parent_names_ao[] = {

	"bi_tcxo_ao",

	"core_bi_pll_test_se",

};



static const struct parent_map disp_cc_parent_map_3[] = {

	{ P_BI_TCXO, 0 },

	{ P_DISP_CC_PLL0_OUT_MAIN, 1 },
@@ -562,13 +567,9 @@ static struct clk_rcg2 disp_cc_xo_clk_src = { 
	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "disp_cc_xo_clk_src",

		.parent_names = disp_cc_parent_names_2,

		.parent_names = disp_cc_parent_names_ao,

		.num_parents = 2,

		.ops = &clk_rcg2_ops,

		.vdd_class = &vdd_cx,

		.num_rate_max = VDD_NUM,

		.rate_max = (unsigned long[VDD_NUM]) {

			[VDD_LOWER] = 19200000},

	},

};

drivers/clk/qcom/gcc-sdmmagpie.c

+4 −2
Original line number Diff line number Diff line
@@ -1504,7 +1504,7 @@ static struct clk_branch gcc_disp_gpll0_div_clk_src = { 
		.hw.init = &(struct clk_init_data){

			.name = "gcc_disp_gpll0_div_clk_src",

			.parent_names = (const char *[]){

				"gcc_gpll0_main_div_cdiv",

				"gcc_pll0_main_div_cdiv",

			},

			.num_parents = 1,

			.ops = &clk_branch2_ops,
@@ -1646,7 +1646,7 @@ static struct clk_branch gcc_gpu_gpll0_div_clk_src = { 
		.hw.init = &(struct clk_init_data){

			.name = "gcc_gpu_gpll0_div_clk_src",

			.parent_names = (const char *[]){

				"gcc_gpll0_main_div_cdiv",

				"gcc_pll0_main_div_cdiv",

			},

			.num_parents = 1,

			.ops = &clk_branch2_ops,
@@ -2674,6 +2674,7 @@ static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = { 
};



static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {

	.halt_reg = 0x7701c,

	.halt_check = BRANCH_HALT_SKIP,

	.clkr = {

		.enable_reg = 0x7701c,
@@ -2686,6 +2687,7 @@ static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { 
};



static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {

	.halt_reg = 0x77018,

	.halt_check = BRANCH_HALT_SKIP,

	.clkr = {

		.enable_reg = 0x77018,

drivers/clk/qcom/videocc-sdmmagpie.c

+1 −1
Original line number Diff line number Diff line
@@ -68,7 +68,7 @@ static const struct parent_map video_cc_parent_map_2[] = { 
};



static const char * const video_cc_parent_names_2[] = {

	"bi_tcxo",

	"bi_tcxo_ao",

	"core_bi_pll_test_se",

};