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Commit 57ea67b7 authored by Sriharsha Allenki's avatar Sriharsha Allenki
Browse files

usb: phy: Enable proper DP DM masks for PHY interrupts 



Enable proper DP and DM toggle masks to get PHY wakeup
interrupts on DP/DM state changes in different
bus speeds (FS/HS or LS).
Also make sure that the interrupts are cleared by adding
a delay of 200us to prevent an unwanted interrupt that is
triggered during suspend on peripheral disconnect.


Change-Id: I31b9e50dcc47605fd68b691ed3326136527613ad
Signed-off-by: default avatarSriharsha Allenki <sallenki@codeaurora.org>
parent aa64dad6

drivers/usb/phy/phy-qcom-snps-28nm-hs.c

+14 −1
Original line number Diff line number Diff line
@@ -377,8 +377,20 @@ static void msm_snps_hsphy_enable_hv_interrupts(struct msm_snps_hsphy *phy) 
	usleep_range(200, 220);

	writeb_relaxed(0x01, USB2_PHY_USB_PHY_IRQ_CMD);



	/* Make sure the interrupts are cleared */

	usleep_range(200, 220);



	val = readl_relaxed(USB2_PHY_USB_PHY_INTERRUPT_MASK0);

	val |= USB2_PHY_USB_PHY_DPDM_0_1_MASK;

	if (phy->phy.flags & PHY_HSFS_MODE) {

		val |= USB2_PHY_USB_PHY_DP_1_0_MASK |

			USB2_PHY_USB_PHY_DM_0_1_MASK;

	} else if (phy->phy.flags & PHY_LS_MODE) {

		val |= USB2_PHY_USB_PHY_DP_0_1_MASK |

			USB2_PHY_USB_PHY_DM_1_0_MASK;

	} else {

		val |= USB2_PHY_USB_PHY_DP_0_1_MASK |

			USB2_PHY_USB_PHY_DM_0_1_MASK;

	}

	writeb_relaxed(val, USB2_PHY_USB_PHY_INTERRUPT_MASK0);

}
@@ -399,6 +411,7 @@ static void msm_snps_hsphy_disable_hv_interrupts(struct msm_snps_hsphy *phy) 
	writeb_relaxed(0x00, USB2_PHY_USB_PHY_IRQ_CMD);

	usleep_range(200, 220);

	writeb_relaxed(0x01, USB2_PHY_USB_PHY_IRQ_CMD);

	usleep_range(200, 220);

}



static int msm_snps_hsphy_set_suspend(struct usb_phy *uphy, int suspend)

include/linux/usb/msm_hsusb_hw.h

+4 −1
Original line number Diff line number Diff line
@@ -95,7 +95,10 @@ 
#define USB2_PHY_USB_PHY_INTERRUPT_CLEAR1 (MSM_USB_PHY_CSR_BASE + 0x0E0)



#define USB2_PHY_USB_PHY_INTERRUPT_MASK0 (MSM_USB_PHY_CSR_BASE + 0x0D4)

#define USB2_PHY_USB_PHY_DPDM_0_1_MASK		0x0A

#define USB2_PHY_USB_PHY_DP_1_0_MASK		BIT(4)

#define USB2_PHY_USB_PHY_DP_0_1_MASK		BIT(3)

#define USB2_PHY_USB_PHY_DM_1_0_MASK		BIT(2)

#define USB2_PHY_USB_PHY_DM_0_1_MASK		BIT(1)



#define USB2_PHY_USB_PHY_INTERRUPT_MASK1 (MSM_USB_PHY_CSR_BASE + 0x0D8)