Loading Makefile +2 −2 Original line number Diff line number Diff line # SPDX-License-Identifier: GPL-2.0 VERSION = 4 PATCHLEVEL = 14 SUBLEVEL = 0 SUBLEVEL = 2 EXTRAVERSION = NAME = Fearless Coyote NAME = Petit Gorille # *DOCUMENTATION* # To see a list of typical targets execute "make help" Loading arch/sparc/include/asm/cmpxchg_32.h +3 −0 Original line number Diff line number Diff line Loading @@ -63,6 +63,9 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new_, int size) (unsigned long)_n_, sizeof(*(ptr))); \ }) u64 __cmpxchg_u64(u64 *ptr, u64 old, u64 new); #define cmpxchg64(ptr, old, new) __cmpxchg_u64(ptr, old, new) #include <asm-generic/cmpxchg-local.h> /* Loading arch/sparc/include/asm/mmu_context_64.h +2 −0 Original line number Diff line number Diff line Loading @@ -8,9 +8,11 @@ #include <linux/spinlock.h> #include <linux/mm_types.h> #include <linux/smp.h> #include <asm/spitfire.h> #include <asm-generic/mm_hooks.h> #include <asm/percpu.h> static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) { Loading arch/sparc/include/asm/tsb.h +1 −1 Original line number Diff line number Diff line Loading @@ -217,7 +217,7 @@ extern struct tsb_phys_patch_entry __tsb_phys_patch, __tsb_phys_patch_end; sllx REG2, 32, REG2; \ andcc REG1, REG2, %g0; \ be,pt %xcc, 700f; \ sethi %hi(0x1ffc0000), REG2; \ sethi %hi(0xffe00000), REG2; \ sllx REG2, 1, REG2; \ brgez,pn REG1, FAIL_LABEL; \ andn REG1, REG2, REG1; \ Loading arch/sparc/lib/atomic32.c +14 −0 Original line number Diff line number Diff line Loading @@ -173,6 +173,20 @@ unsigned long __cmpxchg_u32(volatile u32 *ptr, u32 old, u32 new) } EXPORT_SYMBOL(__cmpxchg_u32); u64 __cmpxchg_u64(u64 *ptr, u64 old, u64 new) { unsigned long flags; u64 prev; spin_lock_irqsave(ATOMIC_HASH(ptr), flags); if ((prev = *ptr) == old) *ptr = new; spin_unlock_irqrestore(ATOMIC_HASH(ptr), flags); return prev; } EXPORT_SYMBOL(__cmpxchg_u64); unsigned long __xchg_u32(volatile u32 *ptr, u32 new) { unsigned long flags; Loading Loading
Makefile +2 −2 Original line number Diff line number Diff line # SPDX-License-Identifier: GPL-2.0 VERSION = 4 PATCHLEVEL = 14 SUBLEVEL = 0 SUBLEVEL = 2 EXTRAVERSION = NAME = Fearless Coyote NAME = Petit Gorille # *DOCUMENTATION* # To see a list of typical targets execute "make help" Loading
arch/sparc/include/asm/cmpxchg_32.h +3 −0 Original line number Diff line number Diff line Loading @@ -63,6 +63,9 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new_, int size) (unsigned long)_n_, sizeof(*(ptr))); \ }) u64 __cmpxchg_u64(u64 *ptr, u64 old, u64 new); #define cmpxchg64(ptr, old, new) __cmpxchg_u64(ptr, old, new) #include <asm-generic/cmpxchg-local.h> /* Loading
arch/sparc/include/asm/mmu_context_64.h +2 −0 Original line number Diff line number Diff line Loading @@ -8,9 +8,11 @@ #include <linux/spinlock.h> #include <linux/mm_types.h> #include <linux/smp.h> #include <asm/spitfire.h> #include <asm-generic/mm_hooks.h> #include <asm/percpu.h> static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) { Loading
arch/sparc/include/asm/tsb.h +1 −1 Original line number Diff line number Diff line Loading @@ -217,7 +217,7 @@ extern struct tsb_phys_patch_entry __tsb_phys_patch, __tsb_phys_patch_end; sllx REG2, 32, REG2; \ andcc REG1, REG2, %g0; \ be,pt %xcc, 700f; \ sethi %hi(0x1ffc0000), REG2; \ sethi %hi(0xffe00000), REG2; \ sllx REG2, 1, REG2; \ brgez,pn REG1, FAIL_LABEL; \ andn REG1, REG2, REG1; \ Loading
arch/sparc/lib/atomic32.c +14 −0 Original line number Diff line number Diff line Loading @@ -173,6 +173,20 @@ unsigned long __cmpxchg_u32(volatile u32 *ptr, u32 old, u32 new) } EXPORT_SYMBOL(__cmpxchg_u32); u64 __cmpxchg_u64(u64 *ptr, u64 old, u64 new) { unsigned long flags; u64 prev; spin_lock_irqsave(ATOMIC_HASH(ptr), flags); if ((prev = *ptr) == old) *ptr = new; spin_unlock_irqrestore(ATOMIC_HASH(ptr), flags); return prev; } EXPORT_SYMBOL(__cmpxchg_u64); unsigned long __xchg_u32(volatile u32 *ptr, u32 new) { unsigned long flags; Loading