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Commit 56fbf600 authored by Robin Murphy's avatar Robin Murphy Committed by Will Deacon
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iommu/arm-smmu: Add global SMR masking property 



The current SMR masking support using a 2-cell iommu-specifier is
primarily intended to handle individual masters with large and/or
complex Stream ID assignments; it quickly gets a bit clunky in other SMR
use-cases where we just want to consistently mask out the same part of
every Stream ID (e.g. for MMU-500 configurations where the appended TBU
number gets in the way unnecessarily). Let's add a new property to allow
a single global mask value to better fit the latter situation.

Acked-by: default avatarMark Rutland <mark.rutland@arm.com>
Tested-by: default avatarNipun Gupta <nipun.gupta@nxp.com>
Signed-off-by: default avatarRobin Murphy <robin.murphy@arm.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent 8513c893

Documentation/devicetree/bindings/iommu/arm,smmu.txt

+28 −0
Original line number Diff line number Diff line
@@ -60,6 +60,17 @@ conditions. 
                  aliases of secure registers have to be used during

                  SMMU configuration.



- stream-match-mask : For SMMUs supporting stream matching and using

                  #iommu-cells = <1>, specifies a mask of bits to ignore

		  when matching stream IDs (e.g. this may be programmed

		  into the SMRn.MASK field of every stream match register

		  used). For cases where it is desirable to ignore some

                  portion of every Stream ID (e.g. for certain MMU-500

                  configurations given globally unique input IDs). This

                  property is not valid for SMMUs using stream indexing,

                  or using stream matching with #iommu-cells = <2>, and

                  may be ignored if present in such cases.



** Deprecated properties:



- mmu-masters (deprecated in favour of the generic "iommus" binding) :
@@ -109,3 +120,20 @@ conditions. 
        master3 {

                iommus = <&smmu2 1 0x30>;

        };





        /* ARM MMU-500 with 10-bit stream ID input configuration */

        smmu3: iommu {

                compatible = "arm,mmu-500", "arm,smmu-v2";

                ...

                #iommu-cells = <1>;

                /* always ignore appended 5-bit TBU number */

                stream-match-mask = 0x7c00;

        };



        bus {

                /* bus whose child devices emit one unique 10-bit stream

                   ID each, but may master through multiple SMMU TBUs */

                iommu-map = <0 &smmu3 0 0x400>;

                ...

        };

drivers/iommu/arm-smmu.c

+3 −1
Original line number Diff line number Diff line
@@ -1644,13 +1644,15 @@ static int arm_smmu_domain_set_attr(struct iommu_domain *domain, 


static int arm_smmu_of_xlate(struct device *dev, struct of_phandle_args *args)

{

	u32 fwid = 0;

	u32 mask, fwid = 0;



	if (args->args_count > 0)

		fwid |= (u16)args->args[0];



	if (args->args_count > 1)

		fwid |= (u16)args->args[1] << SMR_MASK_SHIFT;

	else if (!of_property_read_u32(args->np, "stream-match-mask", &mask))

		fwid |= (u16)mask << SMR_MASK_SHIFT;



	return iommu_fwspec_add_ids(dev, &fwid, 1);

}