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Commit 56b60b8b authored by Tomasz Figa's avatar Tomasz Figa Committed by Russell King
Browse files

ARM: 8265/1: dts: exynos4: Add nodes for L2 cache controller 



This patch adds device tree nodes for L2 cache controller present on
Exynos4 SoCs.

Signed-off-by: default avatarTomasz Figa <t.figa@samsung.com>
Signed-off-by: default avatarMarek Szyprowski <m.szyprowski@samsung.com>
Acked-by: default avatarArnd Bergmann <arnd@arndb.de>
Acked-by: default avatarKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 30ad527a

arch/arm/boot/dts/exynos4210.dtsi

+9 −0
Original line number Diff line number Diff line
@@ -81,6 +81,15 @@ 
		reg = <0x10023CA0 0x20>;

	};



	l2c: l2-cache-controller@10502000 {

		compatible = "arm,pl310-cache";

		reg = <0x10502000 0x1000>;

		cache-unified;

		cache-level = <2>;

		arm,tag-latency = <2 2 1>;

		arm,data-latency = <2 2 1>;

	};



	gic: interrupt-controller@10490000 {

		cpu-offset = <0x8000>;

	};

arch/arm/boot/dts/exynos4x12.dtsi

+14 −0
Original line number Diff line number Diff line
@@ -54,6 +54,20 @@ 
		reg = <0x10023CA0 0x20>;

	};



	l2c: l2-cache-controller@10502000 {

		compatible = "arm,pl310-cache";

		reg = <0x10502000 0x1000>;

		cache-unified;

		cache-level = <2>;

		arm,tag-latency = <2 2 1>;

		arm,data-latency = <3 2 1>;

		arm,double-linefill = <1>;

		arm,double-linefill-incr = <0>;

		arm,double-linefill-wrap = <1>;

		arm,prefetch-drop = <1>;

		arm,prefetch-offset = <7>;

	};



	clock: clock-controller@10030000 {

		compatible = "samsung,exynos4412-clock";

		reg = <0x10030000 0x20000>;