Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 56b3152e authored by Anish Bhatt's avatar Anish Bhatt Committed by Greg Kroah-Hartman
Browse files

rtl8192u: BIT() macro cleanup 



Use the BIT(x) macro directly instead using multiple
BITX defines.

Signed-off-by: default avatarAnish Bhatt <anish@gatech.edu>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent eb36cc28

drivers/staging/rtl8192u/ieee80211/ieee80211.h

+5 −5
Original line number Diff line number Diff line
@@ -415,7 +415,7 @@ typedef struct ieee_param { 
/* QOS control */

#define IEEE80211_QCTL_TID              0x000F



#define	FC_QOS_BIT					BIT7

#define	FC_QOS_BIT					BIT(7)

#define IsDataFrame(pdu)			( ((pdu[0] & 0x0C)==0x08) ? true : false )

#define	IsLegacyDataFrame(pdu)	(IsDataFrame(pdu) && (!(pdu[0]&FC_QOS_BIT)) )

//added by wb. Is this right?
@@ -1565,10 +1565,10 @@ typedef struct _RT_POWER_SAVE_CONTROL { 
} RT_POWER_SAVE_CONTROL, *PRT_POWER_SAVE_CONTROL;



typedef u32 RT_RF_CHANGE_SOURCE;

#define RF_CHANGE_BY_SW BIT31

#define RF_CHANGE_BY_HW BIT30

#define RF_CHANGE_BY_PS BIT29

#define RF_CHANGE_BY_IPS BIT28

#define RF_CHANGE_BY_SW		BIT(31)

#define RF_CHANGE_BY_HW		BIT(30)

#define RF_CHANGE_BY_PS		BIT(29)

#define RF_CHANGE_BY_IPS	BIT(28)

#define RF_CHANGE_BY_INIT	0	// Do not change the RFOff reason. Defined by Bruce, 2008-01-17.



typedef enum

drivers/staging/rtl8192u/ieee80211/rtl819x_Qos.h

+8 −41
Original line number Diff line number Diff line 
#ifndef __INC_QOS_TYPE_H

#define __INC_QOS_TYPE_H



#define BIT0                    0x00000001

#define BIT1                    0x00000002

#define BIT2                    0x00000004

#define BIT3                    0x00000008

#define BIT4                    0x00000010

#define BIT5                    0x00000020

#define BIT6                    0x00000040

#define BIT7                    0x00000080

#define BIT8                    0x00000100

#define BIT9                    0x00000200

#define BIT10                   0x00000400

#define BIT11                   0x00000800

#define BIT12                   0x00001000

#define BIT13                   0x00002000

#define BIT14                   0x00004000

#define BIT15                   0x00008000

#define BIT16                   0x00010000

#define BIT17                   0x00020000

#define BIT18                   0x00040000

#define BIT19                   0x00080000

#define BIT20                   0x00100000

#define BIT21                   0x00200000

#define BIT22                   0x00400000

#define BIT23                   0x00800000

#define BIT24                   0x01000000

#define BIT25                   0x02000000

#define BIT26                   0x04000000

#define BIT27                   0x08000000

#define BIT28                   0x10000000

#define BIT29                   0x20000000

#define BIT30                   0x40000000

#define BIT31                   0x80000000



#define	MAX_WMMELE_LENGTH	64



//
@@ -375,17 +342,17 @@ typedef struct _ACM{ 


typedef	u8		AC_UAPSD, *PAC_UAPSD;



#define	GET_VO_UAPSD(_apsd) ((_apsd) & BIT0)

#define	SET_VO_UAPSD(_apsd) ((_apsd) |= BIT0)

#define	GET_VO_UAPSD(_apsd) ((_apsd) & BIT(0))

#define	SET_VO_UAPSD(_apsd) ((_apsd) |= BIT(0))



#define	GET_VI_UAPSD(_apsd) ((_apsd) & BIT1)

#define	SET_VI_UAPSD(_apsd) ((_apsd) |= BIT1)

#define	GET_VI_UAPSD(_apsd) ((_apsd) & BIT(1))

#define	SET_VI_UAPSD(_apsd) ((_apsd) |= BIT(1))



#define	GET_BK_UAPSD(_apsd) ((_apsd) & BIT2)

#define	SET_BK_UAPSD(_apsd) ((_apsd) |= BIT2)

#define	GET_BK_UAPSD(_apsd) ((_apsd) & BIT(2))

#define	SET_BK_UAPSD(_apsd) ((_apsd) |= BIT(2))



#define	GET_BE_UAPSD(_apsd) ((_apsd) & BIT3)

#define	SET_BE_UAPSD(_apsd) ((_apsd) |= BIT3)

#define	GET_BE_UAPSD(_apsd) ((_apsd) & BIT(3))

#define	SET_BE_UAPSD(_apsd) ((_apsd) |= BIT(3))





//typedef struct _TCLASS{

drivers/staging/rtl8192u/r8192U.h

+31 −64
Original line number Diff line number Diff line
@@ -43,39 +43,6 @@ 
#define MAX_KEY_LEN     61

#define KEY_BUF_SIZE    5



#define BIT0            0x00000001

#define BIT1            0x00000002

#define BIT2            0x00000004

#define BIT3            0x00000008

#define BIT4            0x00000010

#define BIT5            0x00000020

#define BIT6            0x00000040

#define BIT7            0x00000080

#define BIT8            0x00000100

#define BIT9            0x00000200

#define BIT10           0x00000400

#define BIT11           0x00000800

#define BIT12           0x00001000

#define BIT13           0x00002000

#define BIT14           0x00004000

#define BIT15           0x00008000

#define BIT16           0x00010000

#define BIT17           0x00020000

#define BIT18           0x00040000

#define BIT19           0x00080000

#define BIT20           0x00100000

#define BIT21           0x00200000

#define BIT22           0x00400000

#define BIT23           0x00800000

#define BIT24           0x01000000

#define BIT25           0x02000000

#define BIT26           0x04000000

#define BIT27           0x08000000

#define BIT28           0x10000000

#define BIT29           0x20000000

#define BIT30           0x40000000

#define BIT31           0x80000000



#define	Rx_Smooth_Factor		20

#define DMESG(x, a...)

#define DMESGW(x, a...)
@@ -87,44 +54,44 @@ extern u32 rt_global_debug_component; 
			pr_debug("RTL8192U: " x "\n", ##args);	\

	} while (0)



#define COMP_TRACE              BIT0  /* Function call tracing. */

#define COMP_DBG                BIT1

#define COMP_INIT               BIT2  /* Driver initialization/halt/reset. */

#define COMP_TRACE              BIT(0)  /* Function call tracing. */

#define COMP_DBG                BIT(1)

#define COMP_INIT               BIT(2)  /* Driver initialization/halt/reset. */





#define COMP_RECV               BIT3  /* Receive data path. */

#define COMP_SEND               BIT4  /* Send data path. */

#define COMP_IO                 BIT5

#define COMP_RECV               BIT(3)  /* Receive data path. */

#define COMP_SEND               BIT(4)  /* Send data path. */

#define COMP_IO                 BIT(5)

/* 802.11 Power Save mode or System/Device Power state. */

#define COMP_POWER              BIT6

#define COMP_POWER              BIT(6)

/* 802.11 link related: join/start BSS, leave BSS. */

#define COMP_EPROM              BIT7

#define COMP_SWBW               BIT8  /* Bandwidth switch. */

#define COMP_POWER_TRACKING     BIT9  /* 8190 TX Power Tracking */

#define COMP_TURBO              BIT10 /* Turbo Mode */

#define COMP_QOS                BIT11

#define COMP_RATE               BIT12 /* Rate Adaptive mechanism */

#define COMP_RM                 BIT13 /* Radio Measurement */

#define COMP_DIG                BIT14

#define COMP_PHY                BIT15

#define COMP_CH                 BIT16 /* Channel setting debug */

#define COMP_TXAGC              BIT17 /* Tx power */

#define COMP_HIPWR              BIT18 /* High Power Mechanism */

#define COMP_HALDM              BIT19 /* HW Dynamic Mechanism */

#define COMP_SEC                BIT20 /* Event handling */

#define COMP_LED                BIT21

#define COMP_RF                 BIT22

#define COMP_RXDESC             BIT23 /* Rx desc information for SD3 debug */

#define COMP_EPROM              BIT(7)

#define COMP_SWBW               BIT(8)  /* Bandwidth switch. */

#define COMP_POWER_TRACKING     BIT(9)  /* 8190 TX Power Tracking */

#define COMP_TURBO              BIT(10) /* Turbo Mode */

#define COMP_QOS                BIT(11)

#define COMP_RATE               BIT(12) /* Rate Adaptive mechanism */

#define COMP_RM                 BIT(13) /* Radio Measurement */

#define COMP_DIG                BIT(14)

#define COMP_PHY                BIT(15)

#define COMP_CH                 BIT(16) /* Channel setting debug */

#define COMP_TXAGC              BIT(17) /* Tx power */

#define COMP_HIPWR              BIT(18) /* High Power Mechanism */

#define COMP_HALDM              BIT(19) /* HW Dynamic Mechanism */

#define COMP_SEC                BIT(20) /* Event handling */

#define COMP_LED                BIT(21)

#define COMP_RF                 BIT(22)

#define COMP_RXDESC             BIT(23) /* Rx desc information for SD3 debug */



/* 11n or 8190 specific code */



#define COMP_FIRMWARE           BIT24 /* Firmware downloading */

#define COMP_HT                 BIT25 /* 802.11n HT related information */

#define COMP_AMSDU              BIT26 /* A-MSDU Debugging */

#define COMP_SCAN               BIT27

#define COMP_DOWN               BIT29 /* rm driver module */

#define COMP_RESET              BIT30 /* Silent reset */

#define COMP_ERR                BIT31 /* Error out, always on */

#define COMP_FIRMWARE           BIT(24) /* Firmware downloading */

#define COMP_HT                 BIT(25) /* 802.11n HT related information */

#define COMP_AMSDU              BIT(26) /* A-MSDU Debugging */

#define COMP_SCAN               BIT(27)

#define COMP_DOWN               BIT(29) /* rm driver module */

#define COMP_RESET              BIT(30) /* Silent reset */

#define COMP_ERR                BIT(31) /* Error out, always on */



#define RTL819x_DEBUG

#ifdef RTL819x_DEBUG

drivers/staging/rtl8192u/r8192U_core.c

+6 −6
Original line number Diff line number Diff line
@@ -233,7 +233,7 @@ static void CamResetAllEntry(struct net_device *dev) 
	 * condition, Cam can not be reset because upper layer will not set

	 * this static key again.

	 */

	ulcommand |= BIT31 | BIT30;

	ulcommand |= BIT(31) | BIT(30);

	write_nic_dword(dev, RWCAM, ulcommand);



}
@@ -242,7 +242,7 @@ static void CamResetAllEntry(struct net_device *dev) 
void write_cam(struct net_device *dev, u8 addr, u32 data)

{

	write_nic_dword(dev, WCAMI, data);

	write_nic_dword(dev, RWCAM, BIT31 | BIT16 | (addr & 0xff));

	write_nic_dword(dev, RWCAM, BIT(31) | BIT(16) | (addr & 0xff));

}



u32 read_cam(struct net_device *dev, u8 addr)
@@ -2412,7 +2412,7 @@ static void rtl8192_get_eeprom_size(struct net_device *dev) 
	read_nic_word_E(dev, EPROM_CMD, &curCR);

	RT_TRACE(COMP_EPROM,

		 "read from Reg EPROM_CMD(%x):%x\n", EPROM_CMD, curCR);

	/* whether need I consider BIT5? */

	/* whether need I consider BIT(5?) */

	priv->epromtype =

		(curCR & Cmd9346CR_9356SEL) ? EPROM_93c56 : EPROM_93c46;

	RT_TRACE(COMP_EPROM,
@@ -5180,14 +5180,14 @@ void setKey(struct net_device *dev, u8 EntryNo, u8 KeyIndex, u16 KeyType, 
		 dev, EntryNo, KeyIndex, KeyType, MacAddr);



	if (DefaultKey)

		usConfig |= BIT15 | (KeyType << 2);

		usConfig |= BIT(15) | (KeyType << 2);

	else

		usConfig |= BIT15 | (KeyType << 2) | KeyIndex;

		usConfig |= BIT(15) | (KeyType << 2) | KeyIndex;





	for (i = 0; i < CAM_CONTENT_COUNT; i++) {

		TargetCommand  = i + CAM_CONTENT_COUNT * EntryNo;

		TargetCommand |= BIT31 | BIT16;

		TargetCommand |= BIT(31) | BIT(16);



		if (i == 0) { /* MAC|Config */

			TargetContent = (u32)(*(MacAddr + 0)) << 16 |

drivers/staging/rtl8192u/r8192U_dm.c

+11 −6
Original line number Diff line number Diff line
@@ -325,21 +325,26 @@ static void dm_check_rate_adaptive(struct net_device *dev) 
			(!pHTInfo->bCurTxBW40MHz && pHTInfo->bCurShortGI20MHz);



		pra->upper_rssi_threshold_ratr =

				(pra->upper_rssi_threshold_ratr & (~BIT31)) | ((bshort_gi_enabled) ? BIT31:0);

				(pra->upper_rssi_threshold_ratr & (~BIT(31))) |

				((bshort_gi_enabled) ? BIT(31) : 0);



		pra->middle_rssi_threshold_ratr =

				(pra->middle_rssi_threshold_ratr & (~BIT31)) | ((bshort_gi_enabled) ? BIT31:0);

				(pra->middle_rssi_threshold_ratr & (~BIT(31))) |

				((bshort_gi_enabled) ? BIT(31) : 0);



		if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) {

			pra->low_rssi_threshold_ratr =

				(pra->low_rssi_threshold_ratr_40M & (~BIT31)) | ((bshort_gi_enabled) ? BIT31:0);

			      (pra->low_rssi_threshold_ratr_40M & (~BIT(31))) |

			      ((bshort_gi_enabled) ? BIT(31) : 0);

		} else {

			pra->low_rssi_threshold_ratr =

			(pra->low_rssi_threshold_ratr_20M & (~BIT31)) | ((bshort_gi_enabled) ? BIT31:0);

			(pra->low_rssi_threshold_ratr_20M & (~BIT(31))) |

			((bshort_gi_enabled) ? BIT(31) : 0);

		}

		/* cosa add for test */

		pra->ping_rssi_ratr =

				(pra->ping_rssi_ratr & (~BIT31)) | ((bshort_gi_enabled) ? BIT31:0);

				(pra->ping_rssi_ratr & (~BIT(31))) |

				((bshort_gi_enabled) ? BIT(31) : 0);



		/* 2007/10/08 MH We support RA smooth scheme now. When it is the first

		   time to link with AP. We will not change upper/lower threshold. If
@@ -2378,7 +2383,7 @@ static void dm_check_pbc_gpio(struct net_device *dev) 
	if (tmp1byte == 0xff)

		return;



	if (tmp1byte&BIT6 || tmp1byte&BIT0) {

	if (tmp1byte & BIT(6) || tmp1byte & BIT(0)) {

		/*

		 * Here we only set bPbcPressed to TRUE

		 * After trigger PBC, the variable will be set to FALSE